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joris
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vhdl-prng
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eca4097d59
vhdl-prng
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sim
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Joris van Rantwijk
eca4097d59
Trivium: Add VHDL test bench.
2016-11-28 19:57:42 +01:00
..
Makefile
Trivium: Flip bit-order.
2016-11-24 00:23:35 +01:00
tb_mt19937.vhdl
Minor code cleanup for MT19937 and improve testbench.
2016-11-12 22:40:59 +01:00
tb_trivium.vhdl
Trivium: Add VHDL test bench.
2016-11-28 19:57:42 +01:00
tb_xoroshiro128plus.vhdl
Test bench for Xoroshiro128plus:
2016-10-21 13:54:42 +02:00