108 lines
2.3 KiB
VHDL
108 lines
2.3 KiB
VHDL
--
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-- Monitor min/max sample values from ADC.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity adc_range_monitor is
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generic (
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-- True if ADC samples are signed values.
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-- False if ADC samples are unsigned binary offset values.
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signed_data: boolean
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);
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to clear min/max sample values.
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clear: in std_logic;
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-- Input sample stream.
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in_data: in adc_data_type;
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-- Minimum and maximum sample value observed.
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min_value: out adc_data_type;
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max_value: out adc_data_type
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);
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end entity;
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architecture arch of adc_range_monitor is
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type regs_type is record
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min_value: adc_data_type;
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max_value: adc_data_type;
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end record;
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signal r: regs_type;
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signal rnext: regs_type;
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-- Return True if X is less than Y.
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function sample_less(x: adc_data_type; y: adc_data_type)
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return boolean
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is begin
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if signed_data then
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return signed(x) < signed(y);
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else
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return unsigned(x) < unsigned(y);
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end if;
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end function;
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begin
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-- Drive output.
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min_value <= r.min_value;
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max_value <= r.max_value;
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--
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-- Combinatorial process.
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--
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process (all) is
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variable v: regs_type;
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begin
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-- Load current register values.
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v := r;
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-- Update min value.
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if (reset = '1')
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or (clear = '1')
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or sample_less(in_data, r.min_value) then
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v.min_value := in_data;
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end if;
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-- Update max value.
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if (reset = '1')
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or (clear = '1')
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or sample_less(r.max_value, in_data) then
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v.max_value := in_data;
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end if;
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-- Drive new register values to synchronous process.
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rnext <= v;
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end process;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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r <= rnext;
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end if;
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end process;
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end architecture;
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