91 lines
2.3 KiB
VHDL
91 lines
2.3 KiB
VHDL
--
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-- Signed or unsigned variable right-shift.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity shift_engine is
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generic (
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-- Input word length.
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input_data_bits: integer range 4 to 64;
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-- Output word length.
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output_data_bits: integer range 4 to 64;
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-- Number of bit positions to pre-shift left before shifting right.
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pre_shift_left: integer range 0 to 16;
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-- True to apply sign extension when shifting.
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-- False to apply zero extension.
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signed_data: boolean
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);
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Data input operand.
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-- A new input word is accepted on every clock cycle.
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in_data: in std_logic_vector(input_data_bits - 1 downto 0);
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-- Shift input operand.
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-- It indicates the number of bit positions to shift right, expressed
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-- as an unsigned integer in range 0 to 15.
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-- A new input word is accepted on every clock cycle.
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in_shift: in std_logic_vector(3 downto 0);
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-- Shifted output data.
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-- The output corresponds to the input delayed by 1 clock cycle.
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out_data: out std_logic_vector(output_data_bits - 1 downto 0)
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);
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end entity;
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architecture arch of shift_engine is
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-- Output register.
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signal r_data: std_logic_vector(output_data_bits - 1 downto 0);
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begin
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-- Drive output.
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out_data <= r_data;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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if signed_data then
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r_data <= std_logic_vector(
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shift_right(
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shift_left(
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resize(signed(in_data), output_data_bits),
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pre_shift_left),
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to_integer(unsigned(in_shift))));
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else
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r_data <= std_logic_vector(
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shift_right(
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shift_left(
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resize(unsigned(in_data), output_data_bits),
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pre_shift_left),
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to_integer(unsigned(in_shift))));
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end if;
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end if;
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end process;
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end architecture;
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