575 lines
24 KiB
VHDL
575 lines
24 KiB
VHDL
--
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-- AXI3 master for multi-channel DMA controller.
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--
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-- Note: DMA transfers may not cross a 4 kB address boundary.
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--
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-- It is recommended to use only so-called regular transactions.
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-- A transaction is regular if its length is 1, 2, 4, 8 or 16 beats,
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-- and its address is aligned to the burst length.
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-- Regular transactions never cross a 4 kB boundary.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity dma_axi_master is
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generic (
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-- Number of read channels.
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num_read_channels: integer range 0 to 16;
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-- Number of write channels.
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num_write_channels: integer range 0 to 16
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);
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to enable DMA, low to pause DMA.
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-- When dma_en is low, any ongoing transfer will be completed but no new transfer will be started.
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dma_en: in std_logic;
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-- High while DMA transactions are in progress.
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dma_busy: out std_logic;
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-- Address window in which DMA transaction can occur.
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-- The base address is added to the addresses requested by the channels.
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window_base_addr: in std_logic_vector(31 downto 12);
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window_size: in std_logic_vector(31 downto 12);
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-- Error notifications.
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-- If an error occurs, the corresponding error signal will go high and stay high until cleared.
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-- After error, further DMA transactions will be halted until the error is cleared.
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-- Note that DMA errors will typically cause misalignment of the data flow in client channels.
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err_read: out std_logic; -- AXI slave reported error from read transaction
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err_write: out std_logic; -- AXI slave reported error from write transaction
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err_address: out std_logic; -- Channel requested address outside window
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err_any: out std_logic; -- Logical OR of all error signals
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-- High to clear error notifications.
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clear_errors: in std_logic;
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-- Read channels.
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-- The client passes a read command for a specified address via valid/ready handshake.
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-- Some time later, the controller pushes (read_cmd_length + 1) data words out to the channel.
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-- The client must be ready to accept all data words.
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-- Multiple transfers can be in flight for the channel.
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read_cmd_addr: in dma_address_array(0 to num_read_channels-1);
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read_cmd_length: in dma_burst_length_array(0 to num_read_channels-1);
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read_cmd_valid: in std_logic_vector(num_read_channels-1 downto 0);
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read_cmd_ready: out std_logic_vector(num_read_channels-1 downto 0);
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read_data: out dma_data_array(0 to num_read_channels-1);
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read_data_valid: out std_logic_vector(num_read_channels-1 downto 0);
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-- Write channels.
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-- The client passes a write command for a specified address via valid/ready handshake.
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-- Some time later, the controller pulls (write_cmd_length + 1) data words from the channel.
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-- The client must supply these data words promptly.
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-- Some more time later, the controller pulses write_finished to indicate that the write has finished.
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-- Multiple transfers can be in flight for the channel.
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write_cmd_addr: in dma_address_array(0 to num_write_channels-1);
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write_cmd_length: in dma_burst_length_array(0 to num_write_channels-1);
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write_cmd_valid: in std_logic_vector(num_write_channels-1 downto 0);
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write_cmd_ready: out std_logic_vector(num_write_channels-1 downto 0);
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write_data: in dma_data_array(0 to num_write_channels-1);
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write_data_ready: out std_logic_vector(num_write_channels-1 downto 0);
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write_finished: out std_logic_vector(num_write_channels-1 downto 0);
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-- AXI3 master.
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m_axi_awid: out std_logic_vector(5 downto 0);
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m_axi_awaddr: out std_logic_vector(31 downto 0);
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m_axi_awlen: out std_logic_vector(3 downto 0);
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m_axi_awsize: out std_logic_vector(2 downto 0);
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m_axi_awburst: out std_logic_vector(1 downto 0);
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m_axi_awlock: out std_logic_vector(1 downto 0);
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m_axi_awcache: out std_logic_vector(3 downto 0);
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m_axi_awprot: out std_logic_vector(2 downto 0);
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m_axi_awqos: out std_logic_vector(3 downto 0);
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m_axi_awvalid: out std_logic;
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m_axi_awready: in std_logic;
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m_axi_wid: out std_logic_vector(5 downto 0);
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m_axi_wdata: out std_logic_vector(63 downto 0);
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m_axi_wstrb: out std_logic_vector(7 downto 0);
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m_axi_wlast: out std_logic;
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m_axi_wvalid: out std_logic;
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m_axi_wready: in std_logic;
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m_axi_bid: in std_logic_vector(5 downto 0);
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m_axi_bresp: in std_logic_vector(1 downto 0);
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m_axi_bvalid: in std_logic;
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m_axi_bready: out std_logic;
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m_axi_arid: out std_logic_vector(5 downto 0);
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m_axi_araddr: out std_logic_vector(31 downto 0);
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m_axi_arlen: out std_logic_vector(3 downto 0);
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m_axi_arsize: out std_logic_vector(2 downto 0);
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m_axi_arburst: out std_logic_vector(1 downto 0);
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m_axi_arlock: out std_logic_vector(1 downto 0);
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m_axi_arcache: out std_logic_vector(3 downto 0);
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m_axi_arprot: out std_logic_vector(2 downto 0);
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m_axi_arqos: out std_logic_vector(3 downto 0);
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m_axi_arvalid: out std_logic;
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m_axi_arready: in std_logic;
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m_axi_rid: in std_logic_vector(5 downto 0);
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m_axi_rdata: in std_logic_vector(63 downto 0);
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m_axi_rresp: in std_logic_vector(1 downto 0);
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m_axi_rlast: in std_logic;
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m_axi_rvalid: in std_logic;
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m_axi_rready: out std_logic
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);
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end entity;
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architecture arch of dma_axi_master is
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type write_state_type is (WRITE_STATE_IDLE, WRITE_STATE_START, WRITE_STATE_FLOW, WRITE_STATE_WAIT);
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type read_state_type is (READ_STATE_IDLE, READ_STATE_START, READ_STATE_WAIT);
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type regs_type is record
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-- Registered output signals to AXI bus.
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awaddr: std_logic_vector(31 downto 3);
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awlen: std_logic_vector(3 downto 0);
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awvalid: std_logic;
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wdata: std_logic_vector(63 downto 0);
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wlast: std_logic;
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wvalid: std_logic;
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araddr: std_logic_vector(31 downto 3);
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arlen: std_logic_vector(3 downto 0);
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arvalid: std_logic;
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-- Registered output signals to read channels.
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read_cmd_ready: std_logic_vector(num_read_channels-1 downto 0);
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read_data: std_logic_vector(63 downto 0);
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read_data_valid: std_logic_vector(num_read_channels-1 downto 0);
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-- Registered output signals to write channels.
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write_cmd_ready: std_logic_vector(num_write_channels-1 downto 0);
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write_finished: std_logic_vector(num_write_channels-1 downto 0);
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-- Registered status output signals.
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dma_busy: std_logic;
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err_read: std_logic;
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err_write: std_logic;
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err_address: std_logic;
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err_any: std_logic;
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-- Write state machine.
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write_state: write_state_type;
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write_channel: integer range 0 to maximum(0, num_write_channels - 1);
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write_channel_mask: std_logic_vector(num_write_channels-1 downto 0);
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cnt_write_beat: unsigned(3 downto 0);
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cnt_write_start: unsigned(5 downto 0);
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cnt_write_end: unsigned(5 downto 0);
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-- Read command state machine.
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read_state: read_state_type;
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read_channel: integer range 0 to maximum(0, num_read_channels - 1);
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cnt_read_start: unsigned(5 downto 0);
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cnt_read_end: unsigned(5 downto 0);
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end record;
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constant regs_init: regs_type := (
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awaddr => (others => '0'),
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awlen => (others => '0'),
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awvalid => '0',
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wdata => (others => '0'),
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wlast => '0',
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wvalid => '0',
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araddr => (others => '0'),
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arlen => (others => '0'),
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arvalid => '0',
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read_cmd_ready => (others => '0'),
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read_data => (others => '0'),
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read_data_valid => (others => '0'),
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write_cmd_ready => (others => '0'),
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write_finished => (others => '0'),
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dma_busy => '0',
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err_read => '0',
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err_write => '0',
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err_address => '0',
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err_any => '0',
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write_state => WRITE_STATE_IDLE,
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write_channel => 0,
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write_channel_mask => (others => '0'),
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cnt_write_beat => (others => '0'),
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cnt_write_start => (others => '0'),
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cnt_write_end => (others => '0'),
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read_state => READ_STATE_IDLE,
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read_channel => 0,
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cnt_read_start => (others => '0'),
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cnt_read_end => (others => '0')
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);
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signal r: regs_type := regs_init;
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signal rnext: regs_type;
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-- Check that the DMA transfer fits inside the address window if it starts at the specified address offset
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function is_valid_dma_address(addr: std_logic_vector(31 downto 3);
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len: std_logic_vector(3 downto 0);
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limit: std_logic_vector(31 downto 12))
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return boolean
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is begin
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return (unsigned(limit) /= 0)
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and (unsigned(addr) < shift_left(resize(unsigned(limit), 29), 9) - unsigned(len));
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end function;
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-- Calculate tha AXI address for a DMA transfer by adding the address offset from the client
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-- to the base address of the DMA window.
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-- Returns the 29 most significant address bits; the 3 least significant bits are presumed to be 0.
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function calc_dma_address(addr: std_logic_vector(31 downto 3);
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base_addr: std_logic_vector(31 downto 12))
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return std_logic_vector
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is begin
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return std_logic_vector(unsigned(addr) + shift_left(resize(unsigned(base_addr), 29), 9));
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end function;
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begin
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-- Drive fixed output signals to AXI bus.
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m_axi_awsize <= "011"; -- always use 64-bit transfers
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m_axi_arsize <= "011"; -- always use 64-bit transfers
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m_axi_awburst <= "01"; -- always use incrementing burst
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m_axi_arburst <= "01"; -- always use incrementing burst
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m_axi_awlock <= "00"; -- normal access
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m_axi_arlock <= "00"; -- normal access
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m_axi_awcache <= "0010"; -- normal memory, non-cacheable, non-bufferable
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m_axi_arcache <= "0010"; -- normal memory, non-cacheable, non-bufferable
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m_axi_awprot <= "000"; -- data access, secure, unprivileged
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m_axi_arprot <= "000"; -- data access, secure, unprivileged
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m_axi_awqos <= "0000"; -- no QoS
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m_axi_arqos <= "0000"; -- no QoS
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m_axi_wstrb <= "11111111"; -- always write all byte lanes
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m_axi_bready <= '1'; -- always ready for write response
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m_axi_rready <= '1'; -- always ready for read response
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-- Drive variable output signals to AXI bus.
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m_axi_awid <= std_logic_vector(to_unsigned(r.write_channel, 6));
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m_axi_awaddr <= r.awaddr & "000"; -- addresses are 8-byte aligned
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m_axi_awlen <= r.awlen;
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m_axi_awvalid <= r.awvalid;
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m_axi_wid <= std_logic_vector(to_unsigned(r.write_channel, 6));
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m_axi_wdata <= r.wdata;
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m_axi_wlast <= r.wlast;
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m_axi_wvalid <= r.wvalid;
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m_axi_arid <= std_logic_vector(to_unsigned(r.read_channel, 6));
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m_axi_araddr <= r.araddr & "000"; -- addresses are 8-byte aligned
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m_axi_arlen <= r.arlen;
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m_axi_arvalid <= r.arvalid;
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-- Drive output signals to read channels.
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read_cmd_ready <= r.read_cmd_ready;
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read_data_valid <= r.read_data_valid;
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gen_rdata: for ch in 0 to num_read_channels - 1 generate
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read_data(ch) <= r.read_data;
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end generate;
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-- Drive output signals to write channels.
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write_cmd_ready <= r.write_cmd_ready;
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write_finished <= r.write_finished;
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-- Write data ready signalling is complicated:
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-- - During WRITE_STATE_START, one write_data_ready cycle is sent to the selected channel.
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-- - During WRITE_STATE_FLOW, write_data_ready to the selected channel depends asynchronously on AXI wready.
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write_data_ready <=
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r.write_channel_mask
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when ((r.write_state = WRITE_STATE_START) or (r.write_state = WRITE_STATE_FLOW and m_axi_wready = '1'))
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else (others => '0');
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-- Drive output signals.
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dma_busy <= r.dma_busy;
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err_read <= r.err_read;
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err_write <= r.err_write;
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err_address <= r.err_address;
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err_any <= r.err_any;
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--
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-- Combinatorial process.
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--
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process (all) is
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variable v: regs_type;
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begin
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-- Load current register values.
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v := r;
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-- Report DMA busy/idle.
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if (r.cnt_write_start = r.cnt_write_end) and (r.cnt_read_start = r.cnt_read_end) then
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v.dma_busy := '0';
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else
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v.dma_busy := '1';
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end if;
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-- Clear pending errors.
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if clear_errors = '1' then
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v.err_read := '0';
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v.err_write := '0';
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v.err_address := '0';
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v.err_any := '0';
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end if;
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--
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-- Write state machine.
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--
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if num_write_channels > 0 then
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-- By default, do not accept write commands from any channel.
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v.write_cmd_ready := (others => '0');
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-- Maintain one-hot write channel mask for the selected write channel.
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-- This register is needed during WRITE_STATE_START and WRITE_STATE_FLOW.
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v.write_channel_mask := (others => '0');
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v.write_channel_mask(r.write_channel) := '1';
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case r.write_state is
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when WRITE_STATE_IDLE =>
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-- Cycle through write channels until we find a channel that wants to write.
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if (dma_en = '1') and (r.err_any = '0') then
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if write_cmd_valid(r.write_channel) = '1' then
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-- This channel wants to read. Let's do it.
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v.write_state := WRITE_STATE_START;
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v.write_cmd_ready(r.write_channel) := '1';
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v.dma_busy := '1';
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else
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-- Move on to the next channel.
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if r.write_channel >= num_write_channels - 1 then
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v.write_channel := 0;
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else
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v.write_channel := r.write_channel + 1;
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end if;
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end if;
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end if;
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when WRITE_STATE_START =>
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-- Calculate the AXI address by adding the client address offset to the window base address.
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v.awaddr := calc_dma_address(write_cmd_addr(r.write_channel), window_base_addr);
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v.awlen := write_cmd_length(r.write_channel);
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-- Setup first data word.
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v.wdata := write_data(r.write_channel);
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v.cnt_write_beat := unsigned(write_cmd_length(r.write_channel));
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if unsigned(write_cmd_length(r.write_channel)) = 0 then
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v.wlast := '1';
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else
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v.wlast := '0';
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end if;
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-- Check address.
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if is_valid_dma_address(write_cmd_addr(r.write_channel),
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write_cmd_length(r.write_channel),
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window_size) then
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-- Setup AXI write burst.
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v.awvalid := '1';
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v.wvalid := '1';
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v.cnt_write_start := r.cnt_write_start + 1;
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if unsigned(write_cmd_length(r.write_channel)) = 0 then
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v.write_state := WRITE_STATE_WAIT;
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else
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v.write_state := WRITE_STATE_FLOW;
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end if;
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else
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-- Report invalid address.
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-- At this point, the client channel will be stuck with misaligned write command
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-- and data channels, and this write transfer will never be confirmed.
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-- To recover, some type of reset of the client channel will be necessary.
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v.err_address := '1';
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v.err_any := '1';
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v.write_state := WRITE_STATE_IDLE;
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end if;
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-- Mark DMA busy.
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v.dma_busy := '1';
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when WRITE_STATE_FLOW =>
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-- Push subsequent data words to the interconnect.
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-- Drop write command when accepted by interconnect.
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if m_axi_awready = '1' then
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v.awvalid := '0';
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end if;
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-- Push data words to interconnect.
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if m_axi_wready = '1' then
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v.wdata := write_data(r.write_channel);
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if r.cnt_write_beat = 1 then
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-- This will be the last beat of the transfer.
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v.wlast := '1';
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v.write_state := WRITE_STATE_WAIT;
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else
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v.wlast := '0';
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end if;
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v.cnt_write_beat := r.cnt_write_beat - 1;
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end if;
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when WRITE_STATE_WAIT =>
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-- Wait until interconnect accepts the last beat.
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if m_axi_awready = '1' then
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v.awvalid := '0';
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end if;
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if m_axi_wready = '1' then
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v.wvalid := '0';
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end if;
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if (r.awvalid = '0' or m_axi_awready = '1') and (r.wvalid = '0' or m_axi_wready = '1') then
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v.write_state := WRITE_STATE_IDLE;
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end if;
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end case;
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end if;
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--
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-- Handle write completion.
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--
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-- Report write completion to the channel client.
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-- Only successful write bursts are reported.
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-- Note that a write error will cause misalignment between command and data flow in the channel.
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for i in 0 to num_write_channels - 1 loop
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if (m_axi_bvalid = '1') and (m_axi_bresp(1) = '0') and (unsigned(m_axi_bid(3 downto 0)) = i) then
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v.write_finished(i) := '1';
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else
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v.write_finished(i) := '0';
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end if;
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end loop;
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|
|
-- Detect write errors.
|
|
if (m_axi_bvalid = '1') and (m_axi_bresp(1) = '1') then
|
|
v.err_write := '1';
|
|
v.err_any := '1';
|
|
end if;
|
|
|
|
-- Count write burst completed.
|
|
if m_axi_bvalid = '1' then
|
|
v.cnt_write_end := r.cnt_write_end + 1;
|
|
end if;
|
|
|
|
--
|
|
-- Read command state machine.
|
|
--
|
|
|
|
if num_read_channels > 0 then
|
|
|
|
-- By default, do not accept read commands from any channel.
|
|
v.read_cmd_ready := (others => '0');
|
|
|
|
case r.read_state is
|
|
when READ_STATE_IDLE =>
|
|
-- Cycle through read channels until we find a channel that wants to read.
|
|
if (dma_en = '1') and (r.err_any = '0') then
|
|
if read_cmd_valid(r.read_channel) = '1' then
|
|
-- This channel wants to read. Let's do it.
|
|
v.read_state := READ_STATE_START;
|
|
v.read_cmd_ready(r.read_channel) := '1';
|
|
v.dma_busy := '1';
|
|
else
|
|
-- Move on to the next channel.
|
|
if r.read_channel >= num_read_channels - 1 then
|
|
v.read_channel := 0;
|
|
else
|
|
v.read_channel := r.read_channel + 1;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
when READ_STATE_START =>
|
|
|
|
-- Calculate the AXI address by adding the client address offset to the window base address.
|
|
v.araddr := calc_dma_address(read_cmd_addr(r.read_channel), window_base_addr);
|
|
v.arlen := read_cmd_length(r.read_channel);
|
|
|
|
-- Check address.
|
|
if is_valid_dma_address(read_cmd_addr(r.read_channel),
|
|
read_cmd_length(r.read_channel),
|
|
window_size) then
|
|
-- Setup AXI read burst.
|
|
v.arvalid := '1';
|
|
v.read_state := READ_STATE_WAIT;
|
|
else
|
|
-- Report invalid address.
|
|
-- At this point, the client channel will be stuck waiting for results
|
|
-- that are never going to arrive.
|
|
-- To recover, some type of reset of the client channel will be necessary.
|
|
v.err_address := '1';
|
|
v.err_any := '1';
|
|
v.read_state := READ_STATE_IDLE;
|
|
end if;
|
|
|
|
-- Mark DMA busy.
|
|
v.dma_busy := '1';
|
|
|
|
when READ_STATE_WAIT =>
|
|
-- Wait until interconnect accepts our read burst.
|
|
v.dma_busy := '1';
|
|
if m_axi_arready = '1' then
|
|
-- Read burst accepted.
|
|
v.arvalid := '0';
|
|
v.cnt_read_start := r.cnt_read_start + 1;
|
|
v.read_state := READ_STATE_IDLE;
|
|
end if;
|
|
|
|
end case;
|
|
|
|
end if;
|
|
|
|
--
|
|
-- Handle read result.
|
|
--
|
|
|
|
-- Latch read result in a register.
|
|
if m_axi_rvalid = '1' then
|
|
v.read_data := m_axi_rdata;
|
|
end if;
|
|
|
|
-- Report read data to the channel client.
|
|
-- Only successful read results are reported.
|
|
-- Note than a read error will cause misalignment between command and data flow in the channel.
|
|
for i in 0 to num_read_channels - 1 loop
|
|
if (m_axi_rvalid = '1') and (m_axi_rresp(1) = '0') and (unsigned(m_axi_rid(3 downto 0)) = i) then
|
|
v.read_data_valid(i) := '1';
|
|
else
|
|
v.read_data_valid(i) := '0';
|
|
end if;
|
|
end loop;
|
|
|
|
-- Detect read errors.
|
|
if (m_axi_rvalid = '1') and (m_axi_rresp(1) = '1') then
|
|
v.err_read := '1';
|
|
v.err_any := '1';
|
|
end if;
|
|
|
|
-- Count read burst completed.
|
|
if m_axi_rvalid = '1' and m_axi_rlast = '1' then
|
|
v.cnt_read_end := r.cnt_read_end + 1;
|
|
end if;
|
|
|
|
-- Synchronous reset.
|
|
if reset = '1' then
|
|
v := regs_init;
|
|
end if;
|
|
|
|
-- Drive new register values to synchronous process.
|
|
rnext <= v;
|
|
|
|
end process;
|
|
|
|
--
|
|
-- Synchronous process.
|
|
--
|
|
process (clk) is
|
|
begin
|
|
if rising_edge(clk) then
|
|
r <= rnext;
|
|
end if;
|
|
end process;
|
|
|
|
end architecture;
|