Joris van Rantwijk 4814275863 Move trigger inputs to exp_p_io[0 .. 3] ... These inputs are also accessible through the logic analyzer module.		2024-10-10 22:02:44 +02:00
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acquisition_chain.vhd	Add external trigger-once mode	2024-09-24 20:51:02 +02:00
acquisition_manager.vhd	Read digital input signals	2024-08-27 23:48:12 +02:00
acquisition_stream.vhd	Fix 2-channel mode for 4-channel board	2024-10-09 23:06:12 +02:00
adc_capture.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
adc_capture_ddr.vhd	Add support for 4-input Red Pitaya	2024-10-08 08:49:34 +02:00
adc_range_monitor.vhd	Add monitoring of ADC sample and min/max range	2024-08-26 23:11:16 +02:00
adc_sample_stream.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
deglitch.vhd	Read digital input signals	2024-08-27 23:48:12 +02:00
dma_axi_master.vhd	Rework DMA to support single-beat transfers	2024-08-24 23:04:35 +02:00
dma_write_channel.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
ffpair.vhd	Add support for 4-input Red Pitaya	2024-10-08 08:49:34 +02:00
puzzlefw_pkg.vhd	Move trigger inputs to exp_p_io[0 .. 3]	2024-10-10 22:02:44 +02:00
puzzlefw_top.vhd	Move trigger inputs to exp_p_io[0 .. 3]	2024-10-10 22:02:44 +02:00
puzzlefw_top_4ch.vhd	Move trigger inputs to exp_p_io[0 .. 3]	2024-10-10 22:02:44 +02:00
registers.vhd	Add external trigger-once mode	2024-09-24 20:51:02 +02:00
sample_decimation.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
shift_engine.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
simple_fifo.vhd	Add timetagger logic	2024-08-30 23:04:02 +02:00
syncdff.vhd	Read digital input signals	2024-08-27 23:48:12 +02:00
timestamp_gen.vhd	Test analog acquisition chain	2024-08-26 21:31:55 +02:00
timetagger.vhd	Delay timetagger signal to match ADC trigger	2024-09-22 15:01:25 +02:00
trigger_detector.vhd	Add external trigger-once mode	2024-09-24 20:51:02 +02:00