106 lines
2.5 KiB
VHDL
106 lines
2.5 KiB
VHDL
--
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-- Detect external triggers.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity trigger_detector is
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to enable automatic (continuous) triggering.
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trig_auto_en: in std_logic;
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-- High to enable external triggering.
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trig_ext_en: in std_logic;
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-- High to force a trigger event (if the acquisition chain is ready).
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trig_force: in std_logic;
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-- Select external input signal to use as trigger.
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trig_select: in std_logic_vector(1 downto 0);
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-- High to trigger on falling edge, low to trigger on rising edge.
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trig_falling: in std_logic;
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-- Digital input signals.
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trig_ext_in: in std_logic_vector(3 downto 0);
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-- High in the clock cycle following the occurrence of a trigger.
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trig_out: out std_logic
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);
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end entity;
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architecture arch of trigger_detector is
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type regs_type is record
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prev_level: std_logic;
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ext_trig: std_logic;
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trig_out: std_logic;
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end record;
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signal r: regs_type;
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signal rnext: regs_type;
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begin
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-- Drive output.
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trig_out <= r.trig_out;
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--
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-- Combinatorial process.
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--
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process (all) is
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variable v: regs_type;
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begin
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-- Load current register values.
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v := r;
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-- Select external input signal.
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v.prev_level := trig_ext_in(to_integer(unsigned(trig_select)));
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-- Detect active edge.
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v.ext_trig := (not (r.prev_level xor trig_falling)) and
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(v.prev_level xor trig_falling);
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-- Combine trigger sources.
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v.trig_out := trig_auto_en or
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(trig_ext_en and r.ext_trig) or
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trig_force;
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-- Synchronous reset.
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if reset = '1' then
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v.ext_trig := '0';
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v.trig_out := '0';
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end if;
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-- Drive new register values to synchronous process.
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rnext <= v;
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end process;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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r <= rnext;
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end if;
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end process;
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end architecture;
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