58 lines
1.1 KiB
VHDL
58 lines
1.1 KiB
VHDL
--
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-- Generate timestamps.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity timestamp_gen is
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to reset the timestamp counter to 0.
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clear: in std_logic;
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-- Timestamp.
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timestamp: out std_logic_vector(timestamp_bits - 1 downto 0)
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);
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end entity;
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architecture arch of timestamp_gen is
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signal r_counter: unsigned(timestamp_bits - 1 downto 0);
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begin
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-- Drive output.
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timestamp <= std_logic_vector(r_counter);
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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if (reset = '1') or (clear = '1') then
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r_counter <= (others => '0');
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else
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r_counter <= r_counter + 1;
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end if;
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end if;
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end process;
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end architecture;
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