redpitaya-puzzlefw/fpga/vivado
Joris van Rantwijk 716d16e6a3 Test analog acquisition chain 2024-08-26 21:31:55 +02:00
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redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw Disable Hierarchical synthesis of block design 2024-08-03 12:55:22 +02:00
nonproject.tcl Test analog acquisition chain 2024-08-26 21:31:55 +02:00
redpitaya_puzzlefw.xpr Add Vivado project 2024-08-03 12:55:15 +02:00