redpitaya-puzzlefw/fpga/rtl
Joris van Rantwijk 716d16e6a3 Test analog acquisition chain 2024-08-26 21:31:55 +02:00
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acquisition_chain.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
acquisition_manager.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
acquisition_stream.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
adc_capture.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
adc_sample_stream.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
dma_axi_master.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
dma_write_channel.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
puzzlefw_pkg.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
puzzlefw_top.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
registers.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
sample_decimation.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
shift_engine.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
simple_fifo.vhd Add VHDL for DMA write channel 2024-08-09 20:16:53 +02:00
timestamp_gen.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
trigger_detector.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00