240 lines
12 KiB
VHDL
240 lines
12 KiB
VHDL
--
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-- Memory-mapped registers for Red Pitaya PuzzleFW firmware.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity registers is
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- APB bus interface.
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apb_psel: in std_logic;
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apb_penable: in std_logic;
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apb_pwrite: in std_logic;
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apb_paddr: in std_logic_vector(31 downto 0);
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apb_pwdata: in std_logic_vector(31 downto 0);
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apb_pready: out std_logic;
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apb_pslverr: out std_logic;
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apb_prdata: out std_logic_vector(31 downto 0);
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-- FPGA interface.
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reg_control: out registers_control;
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reg_status: in registers_status
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);
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end entity;
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architecture arch of registers is
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type regs_type is record
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pready: std_logic;
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prdata: std_logic_vector(31 downto 0);
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reg_control: registers_control;
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end record;
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constant regs_init: regs_type := (
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pready => '0',
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prdata => (others => '0'),
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reg_control => registers_control_init
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);
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signal r: regs_type := regs_init;
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signal rnext: regs_type;
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begin
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-- Drive output signals.
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apb_pready <= r.pready;
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apb_pslverr <= '0'; -- never signal errors
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apb_prdata <= r.prdata;
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reg_control <= r.reg_control;
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-- Combinatorial process.
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process (all) is
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variable v: regs_type;
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begin
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-- Load current register values.
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v := r;
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-- Clear single-cycle trigger pulses.
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v.reg_control.dma_clear := '0';
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v.reg_control.timestamp_clear := '0';
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v.reg_control.acq_dma_init := '0';
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v.reg_control.acq_intr_clear := '0';
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v.reg_control.trig_force := '0';
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v.reg_control.adc_range_clear := '0';
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v.reg_control.tt_dma_init := '0';
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v.reg_control.tt_intr_clear := '0';
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v.reg_control.timetagger_mark := '0';
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-- Respond to each APB access on the next clock cycle (no wait states).
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v.pready := apb_psel and (not apb_penable);
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-- Handle APB read transfer.
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if apb_psel = '1' and apb_penable = '0' and apb_pwrite = '0' then
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-- Initialize result to all-zero bits.
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v.prdata := (others => '0');
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-- Determine read result as function of address.
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case to_integer(unsigned(apb_paddr and reg_addr_mask)) is
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when reg_info => v.prdata := fw_info_word;
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when reg_irq_enable => v.prdata(0) := r.reg_control.irq_enable;
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when reg_irq_pending => v.prdata(1 downto 0) := reg_status.irq_pending;
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when reg_dma_en => v.prdata(0) := r.reg_control.dma_en;
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when reg_dma_status =>
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v.prdata(0) := reg_status.dma_busy;
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v.prdata(1) := reg_status.dma_err_read;
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v.prdata(2) := reg_status.dma_err_write;
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v.prdata(3) := reg_status.dma_err_address;
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v.prdata(4) := reg_status.dma_err_any;
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when reg_timestamp_lo => v.prdata := reg_status.timestamp(31 downto 0);
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when reg_timestamp_hi => v.prdata(15 downto 0) := reg_status.timestamp(47 downto 32);
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when reg_acq_addr_start => v.prdata(31 downto 7) := r.reg_control.acq_addr_start;
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when reg_acq_addr_end => v.prdata(31 downto 7) := r.reg_control.acq_addr_end;
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when reg_acq_addr_limit => v.prdata(31 downto 7) := r.reg_control.acq_addr_limit;
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when reg_acq_addr_intr => v.prdata(31 downto 3) := r.reg_control.acq_addr_intr;
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when reg_acq_addr_ptr => v.prdata(31 downto 3) := reg_status.acq_addr_ptr;
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when reg_acq_dma_ctrl => v.prdata(0) := r.reg_control.acq_dma_en;
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when reg_acq_intr_ctrl => v.prdata(0) := r.reg_control.acq_intr_en;
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when reg_acq_dma_status => v.prdata(0) := reg_status.acq_dma_busy;
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when reg_acquisition_en => v.prdata(0) := r.reg_control.acquisition_en;
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when reg_record_length => v.prdata(15 downto 0) := r.reg_control.record_length;
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when reg_decimation_factor => v.prdata(17 downto 0) := r.reg_control.decimation_factor;
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when reg_shift_steps => v.prdata(3 downto 0) := r.reg_control.shift_steps;
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when reg_averaging_en => v.prdata(0) := r.reg_control.averaging_en;
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when reg_ch4_mode => v.prdata(0) := r.reg_control.ch4_mode;
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when reg_simulate_adc => v.prdata(0) := r.reg_control.simulate_adc;
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when reg_trigger_mode =>
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v.prdata(0) := r.reg_control.trig_auto_en;
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v.prdata(1) := r.reg_control.trig_ext_en;
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v.prdata(5 downto 4) := r.reg_control.trig_ext_select;
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v.prdata(7) := r.reg_control.trig_ext_falling;
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when reg_trigger_delay => v.prdata(15 downto 0) := r.reg_control.trigger_delay;
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when reg_trigger_status => v.prdata(0) := reg_status.trig_waiting;
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when reg_adc_sample =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_sample(0);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_sample(1);
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when reg_adc23_sample =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_sample(2);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_sample(3);
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when reg_adc0_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(0);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(0);
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when reg_adc1_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(1);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(1);
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when reg_adc2_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(2);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(2);
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when reg_adc3_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(3);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(3);
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when reg_tt_addr_start => v.prdata(31 downto 7) := r.reg_control.tt_addr_start;
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when reg_tt_addr_end => v.prdata(31 downto 7) := r.reg_control.tt_addr_end;
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when reg_tt_addr_limit => v.prdata(31 downto 7) := r.reg_control.tt_addr_limit;
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when reg_tt_addr_intr => v.prdata(31 downto 3) := r.reg_control.tt_addr_intr;
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when reg_tt_addr_ptr => v.prdata(31 downto 3) := reg_status.tt_addr_ptr;
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when reg_tt_dma_ctrl => v.prdata(0) := r.reg_control.tt_dma_en;
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when reg_tt_intr_ctrl => v.prdata(0) := r.reg_control.tt_intr_en;
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when reg_tt_dma_status => v.prdata(0) := reg_status.tt_dma_busy;
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when reg_timetagger_en => v.prdata(7 downto 0) := r.reg_control.timetagger_en;
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when reg_dig_simulate =>
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v.prdata(8) := r.reg_control.dig_simulate;
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v.prdata(3 downto 0) := r.reg_control.dig_sim_state;
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when reg_dig_sample => v.prdata(3 downto 0) := reg_status.dig_sample;
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when reg_led_state => v.prdata(7 downto 0) := r.reg_control.led_state;
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when reg_dma_buf_addr => v.prdata(31 downto 12) := r.reg_control.dma_buf_addr;
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when reg_dma_buf_size => v.prdata(31 downto 12) := r.reg_control.dma_buf_size;
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when others => null;
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end case;
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end if;
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-- Handle APB write transfer.
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if apb_psel = '1' and apb_penable = '0' and apb_pwrite = '1' then
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case to_integer(unsigned(apb_paddr and reg_addr_mask)) is
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when reg_irq_enable => v.reg_control.irq_enable := apb_pwdata(0);
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when reg_dma_en => v.reg_control.dma_en := apb_pwdata(0);
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when reg_dma_clear => v.reg_control.dma_clear := apb_pwdata(0);
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when reg_timestamp_clear => v.reg_control.timestamp_clear := apb_pwdata(0);
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when reg_acq_addr_start => v.reg_control.acq_addr_start := apb_pwdata(31 downto 7);
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when reg_acq_addr_end => v.reg_control.acq_addr_end := apb_pwdata(31 downto 7);
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when reg_acq_addr_limit => v.reg_control.acq_addr_limit := apb_pwdata(31 downto 7);
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when reg_acq_addr_intr => v.reg_control.acq_addr_intr := apb_pwdata(31 downto 3);
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when reg_acq_dma_ctrl =>
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v.reg_control.acq_dma_en := apb_pwdata(0);
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v.reg_control.acq_dma_init := apb_pwdata(1);
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when reg_acq_intr_ctrl =>
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v.reg_control.acq_intr_en := apb_pwdata(0);
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v.reg_control.acq_intr_clear := apb_pwdata(1);
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when reg_acquisition_en => v.reg_control.acquisition_en := apb_pwdata(0);
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when reg_record_length => v.reg_control.record_length := apb_pwdata(15 downto 0);
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when reg_decimation_factor => v.reg_control.decimation_factor := apb_pwdata(17 downto 0);
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when reg_shift_steps => v.reg_control.shift_steps := apb_pwdata(3 downto 0);
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when reg_averaging_en => v.reg_control.averaging_en := apb_pwdata(0);
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when reg_ch4_mode => v.reg_control.ch4_mode := apb_pwdata(0);
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when reg_simulate_adc => v.reg_control.simulate_adc := apb_pwdata(0);
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when reg_trigger_mode =>
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v.reg_control.trig_auto_en := apb_pwdata(0);
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v.reg_control.trig_ext_en := apb_pwdata(1);
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v.reg_control.trig_ext_select := apb_pwdata(5 downto 4);
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v.reg_control.trig_ext_falling := apb_pwdata(7);
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v.reg_control.trig_force := apb_pwdata(8);
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when reg_trigger_delay => v.reg_control.trigger_delay := apb_pwdata(15 downto 0);
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when reg_adc_range_clear => v.reg_control.adc_range_clear := apb_pwdata(0);
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when reg_tt_addr_start => v.reg_control.tt_addr_start := apb_pwdata(31 downto 7);
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when reg_tt_addr_end => v.reg_control.tt_addr_end := apb_pwdata(31 downto 7);
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when reg_tt_addr_limit => v.reg_control.tt_addr_limit := apb_pwdata(31 downto 7);
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when reg_tt_addr_intr => v.reg_control.tt_addr_intr := apb_pwdata(31 downto 3);
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when reg_tt_dma_ctrl =>
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v.reg_control.tt_dma_en := apb_pwdata(0);
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v.reg_control.tt_dma_init := apb_pwdata(1);
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when reg_tt_intr_ctrl =>
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v.reg_control.tt_intr_en := apb_pwdata(0);
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v.reg_control.tt_intr_clear := apb_pwdata(1);
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when reg_timetagger_en => v.reg_control.timetagger_en := apb_pwdata(7 downto 0);
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when reg_timetagger_mark => v.reg_control.timetagger_mark := apb_pwdata(0);
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when reg_dig_simulate =>
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v.reg_control.dig_simulate := apb_pwdata(8);
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v.reg_control.dig_sim_state := apb_pwdata(3 downto 0);
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when reg_led_state => v.reg_control.led_state := apb_pwdata(7 downto 0);
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when reg_dma_buf_addr => v.reg_control.dma_buf_addr := apb_pwdata(31 downto 12);
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when reg_dma_buf_size => v.reg_control.dma_buf_size := apb_pwdata(31 downto 12);
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when others => null;
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end case;
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end if;
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-- Synchronous reset.
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if reset = '1' then
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v := regs_init;
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end if;
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-- Drive new register values to synchronous process.
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rnext <= v;
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end process;
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-- Synchronous process.
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process (clk) is
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begin
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if rising_edge(clk) then
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r <= rnext;
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end if;
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end process;
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end architecture;
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