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redpitaya-puzzlefw
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Alternative, unofficial firmware for the Red Pitaya
98 Commits 2 Branches 0 Tags 951 KiB
VHDL 42.1%
C++ 32.8%
C 10.9%
Shell 7.2%
Tcl 6.8%
Other 0.2%
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Joris van Rantwijk 4d79fecfdc Change FCLK0 frequency to 200 MHz 
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
 		2024-10-06 12:58:11 +02:00
doc Document GPIO and SPI signals to FPGA 2024-10-05 19:12:25 +02:00
fpga Change FCLK0 frequency to 200 MHz 2024-10-06 12:58:11 +02:00
sw Add shell script to configure ADC via SPI 2024-10-05 00:35:20 +02:00