119 lines
3.4 KiB
VHDL
119 lines
3.4 KiB
VHDL
--
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-- Capture ADC sample data from FPGA input ports.
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--
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-- The ADC sends one 14-bit sample per clock cycle.
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-- These 14 bits are transferred through 7 DDR signals.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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use work.puzzlefw_pkg.all;
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entity adc_capture_ddr is
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port (
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-- Source-synchronous clock for capturing data.
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clk_capture: in std_logic;
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-- Clock for intermediate register stage.
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clk_intermediate: in std_logic;
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-- System clock for data output.
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-- This clock is approximately phase aligned with the capture clock.
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clk_handoff: in std_logic;
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-- Input signals, DDR.
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in_data: in std_logic_vector(6 downto 0);
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-- Output sample stream.
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-- Produces one new ADC sample per clock cycle.
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out_data: out adc_data_type
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);
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end entity;
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architecture arch of adc_capture_ddr is
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signal s_data_delayed: std_logic_vector(6 downto 0);
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signal s_data_iddr: std_logic_vector(adc_data_bits - 1 downto 0);
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signal s_data_staged: std_logic_vector(adc_data_bits - 1 downto 0);
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signal r_out_data: std_logic_vector(adc_data_bits - 1 downto 0);
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begin
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gen_bit_capture: for i in 0 to 6 generate
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-- Delay input signal.
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-- Delay by 30 / (32 * 2 * 200 MHz) = 2.34 ns.
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inst_idelay: IDELAYE2
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generic map (
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DELAY_SRC => "IDATAIN",
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HIGH_PERFORMANCE_MODE => "FALSE",
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IDELAY_TYPE => "FIXED",
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IDELAY_VALUE => 30,
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REFCLK_FREQUENCY => 200.0,
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SIGNAL_PATTERN => "DATA" )
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port map (
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CNTVALUEOUT => open,
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DATAOUT => s_data_delayed(i),
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C => '0',
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CE => '0',
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CINVCTRL => '0',
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CNTVALUEIN => (others => '0'),
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DATAIN => '0',
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IDATAIN => in_data(i),
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INC => '0',
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LD => '0',
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LDPIPEEN => '0',
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REGRST => '0' );
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-- DDR input register.
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inst_iddr: IDDR
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generic map (
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DDR_CLK_EDGE => "SAME_EDGE_PIPELINED" )
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port map (
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Q1 => s_data_iddr(2*i),
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Q2 => s_data_iddr(2*i+1),
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C => clk_capture,
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CE => '1',
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D => s_data_delayed(i),
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R => '0',
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S => '0' );
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end generate;
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--
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-- Re-capture samples on intermediate clock.
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--
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gen_ffpair: for i in 0 to adc_data_bits - 1 generate
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inst_ffpair: entity work.ffpair
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port map (
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clk1 => clk_capture,
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clk2 => clk_intermediate,
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di => s_data_iddr(i),
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do => s_data_staged(i) );
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end generate;
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--
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-- Re-capture samples on system clock.
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--
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process (clk_handoff) is
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begin
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if rising_edge(clk_handoff) then
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r_out_data <= s_data_staged;
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end if;
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end process;
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-- Drive output ports.
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out_data <= r_out_data;
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end architecture;
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