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redpitaya-puzzlefw/fpga/vivado
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Joris van Rantwijk 393d87f9d2 Add monitoring of ADC sample and min/max range 2024-08-26 23:11:16 +02:00
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redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw Disable Hierarchical synthesis of block design 2024-08-03 12:55:22 +02:00
nonproject.tcl Add monitoring of ADC sample and min/max range 2024-08-26 23:11:16 +02:00
redpitaya_puzzlefw.xpr Add Vivado project 2024-08-03 12:55:15 +02:00