710 lines
29 KiB
VHDL
710 lines
29 KiB
VHDL
--
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-- Top-level FPGA design for Red Pitaya PuzzleFW firmware,
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-- variant for 4 input channels.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library xpm;
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use xpm.vcomponents.all;
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use work.puzzlefw_pkg.all;
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entity puzzlefw_top_4ch is
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port (
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-- Ports directly connected to ARM/PS.
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DDR_0_addr: inout std_logic_vector(14 downto 0);
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DDR_0_ba: inout std_logic_vector(2 downto 0);
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DDR_0_cas_n: inout std_logic;
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DDR_0_ck_n: inout std_logic;
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DDR_0_ck_p: inout std_logic;
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DDR_0_cke: inout std_logic;
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DDR_0_cs_n: inout std_logic;
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DDR_0_dm: inout std_logic_vector(3 downto 0);
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DDR_0_dq: inout std_logic_vector(31 downto 0);
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DDR_0_dqs_n: inout std_logic_vector(3 downto 0);
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DDR_0_dqs_p: inout std_logic_vector(3 downto 0);
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DDR_0_odt: inout std_logic;
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DDR_0_ras_n: inout std_logic;
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DDR_0_reset_n: inout std_logic;
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DDR_0_we_n: inout std_logic;
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FIXED_IO_0_ddr_vrn: inout std_logic;
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FIXED_IO_0_ddr_vrp: inout std_logic;
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FIXED_IO_0_mio: inout std_logic_vector(53 downto 0);
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FIXED_IO_0_ps_clk: inout std_logic;
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FIXED_IO_0_ps_porb: inout std_logic;
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FIXED_IO_0_ps_srstb: inout std_logic;
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-- Ports controlled by FPGA.
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adc_dat_i: in adc_data_input_type_4ch; -- ADC data
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adc_clk_i: in adc_clock_input_type_4ch; -- ADC clock 1=pos, 0=neg
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spi_csa_o: out std_logic; -- SPI interface to ADC
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spi_csb_o: out std_logic;
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spi_clk_o: out std_logic;
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spi_mosi_o: out std_logic;
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dac_pwm_o: out std_logic_vector(3 downto 0); -- PWM DAC
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exp_p_io: inout std_logic_vector(10 downto 0); -- extension I/O pos
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exp_n_io: inout std_logic_vector(10 downto 0); -- extension I/O neg
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led_o: out std_logic_vector(7 downto 0) -- LEDs
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);
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end puzzlefw_top_4ch;
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architecture arch of puzzlefw_top_4ch is
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-- Main 125 MHz clock, derived from ADC A clock input port.
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signal clk_adc: std_logic;
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-- Auxiliary clock from FCLK0.
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signal clk_fclk200: std_logic;
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-- Reset signals.
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signal s_ext_reset_n: std_logic; -- reset signal from GPIO, active low
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signal s_pll_reset: std_logic; -- reset signal for PLL
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signal s_pll_locked: std_logic; -- PLL locked status
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signal s_reset: std_logic; -- main reset, synchronized to clk_adc
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signal r_reset_done: std_logic; -- reset status report via GPIO
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-- Internal clock signals.
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signal s_adc_clk_ibuf: std_logic_vector(1 downto 0);
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signal clk_adc_capture: std_logic_vector(1 downto 0);
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signal s_pll_clkfbout: std_logic;
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signal s_pll_clkfbin: std_logic;
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signal s_pll_clkout: std_logic;
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-- Blinking LED.
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signal r_adcclk_cnt: unsigned(25 downto 0);
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signal r_adcclk_led: std_logic;
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-- Internal GPIO and SPI signals from PS.
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signal s_gpio_in: std_logic_vector(23 downto 0);
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signal s_gpio_out: std_logic_vector(23 downto 0);
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signal s_spi_sclk_o: std_logic;
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signal s_spi_sclk_t: std_logic;
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signal s_spi_mosi_o: std_logic;
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signal s_spi_mosi_t: std_logic;
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signal s_spi_ss_o: std_logic_vector(1 downto 0);
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signal s_spi_ss_t: std_logic;
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-- APB bus for register access.
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signal s_apb_paddr: std_logic_vector(31 downto 0);
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signal s_apb_penable: std_logic;
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signal s_apb_prdata: std_logic_vector(31 downto 0);
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signal s_apb_pready: std_logic;
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signal s_apb_psel: std_logic;
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signal s_apb_pslverr: std_logic;
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signal s_apb_pwdata: std_logic_vector(31 downto 0);
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signal s_apb_pwrite: std_logic;
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-- AXI bus for DMA.
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signal s_axi_awid: std_logic_vector(5 downto 0);
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signal s_axi_awaddr: std_logic_vector(31 downto 0);
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signal s_axi_awlen: std_logic_vector(3 downto 0);
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signal s_axi_awsize: std_logic_vector(2 downto 0);
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signal s_axi_awburst: std_logic_vector(1 downto 0);
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signal s_axi_awlock: std_logic_vector(1 downto 0);
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signal s_axi_awcache: std_logic_vector(3 downto 0);
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signal s_axi_awprot: std_logic_vector(2 downto 0);
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signal s_axi_awqos: std_logic_vector(3 downto 0);
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signal s_axi_awvalid: std_logic;
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signal s_axi_awready: std_logic;
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signal s_axi_wid: std_logic_vector(5 downto 0);
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signal s_axi_wdata: std_logic_vector(63 downto 0);
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signal s_axi_wstrb: std_logic_vector(7 downto 0);
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signal s_axi_wlast: std_logic;
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signal s_axi_wvalid: std_logic;
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signal s_axi_wready: std_logic;
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signal s_axi_bid: std_logic_vector(5 downto 0);
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signal s_axi_bresp: std_logic_vector(1 downto 0);
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signal s_axi_bvalid: std_logic;
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signal s_axi_bready: std_logic;
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signal s_axi_arid: std_logic_vector(5 downto 0);
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signal s_axi_araddr: std_logic_vector(31 downto 0);
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signal s_axi_arlen: std_logic_vector(3 downto 0);
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signal s_axi_arsize: std_logic_vector(2 downto 0);
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signal s_axi_arburst: std_logic_vector(1 downto 0);
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signal s_axi_arlock: std_logic_vector(1 downto 0);
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signal s_axi_arcache: std_logic_vector(3 downto 0);
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signal s_axi_arprot: std_logic_vector(2 downto 0);
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signal s_axi_arqos: std_logic_vector(3 downto 0);
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signal s_axi_arvalid: std_logic;
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signal s_axi_arready: std_logic;
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signal s_axi_rid: std_logic_vector(5 downto 0);
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signal s_axi_rdata: std_logic_vector(63 downto 0);
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signal s_axi_rresp: std_logic_vector(1 downto 0);
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signal s_axi_rlast: std_logic;
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signal s_axi_rvalid: std_logic;
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signal s_axi_rready: std_logic;
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-- Interrupts.
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signal s_irq_pending: std_logic_vector(1 downto 0);
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signal s_irq_f2p: std_logic_vector(7 downto 0);
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-- Registers.
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signal s_reg_control: registers_control;
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signal s_reg_status: registers_status;
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-- DMA write channel control.
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signal s_dma_write_cmd_addr: dma_address_array(0 to 1);
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signal s_dma_write_cmd_length: dma_burst_length_array(0 to 1);
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signal s_dma_write_cmd_valid: std_logic_vector(1 downto 0);
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signal s_dma_write_cmd_ready: std_logic_vector(1 downto 0);
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signal s_dma_write_data: dma_data_array(0 to 1);
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signal s_dma_write_data_ready: std_logic_vector(1 downto 0);
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signal s_dma_write_finished: std_logic_vector(1 downto 0);
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signal s_acq_dma_valid: std_logic;
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signal s_acq_dma_ready: std_logic;
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signal s_acq_dma_empty: std_logic;
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signal s_acq_dma_data: dma_data_type;
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signal s_tt_dma_valid: std_logic;
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signal s_tt_dma_ready: std_logic;
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signal s_tt_dma_empty: std_logic;
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signal s_tt_dma_data: dma_data_type;
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signal s_timestamp: std_logic_vector(timestamp_bits - 1 downto 0);
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signal s_adc_data: adc_data_array(0 to 3);
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signal s_adc_sample: adc_data_array(0 to 3);
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signal s_dig_in: std_logic_vector(3 downto 0);
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signal s_dig_sync: std_logic_vector(3 downto 0);
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signal s_dig_deglitch: std_logic_vector(3 downto 0);
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signal s_dig_sample: std_logic_vector(3 downto 0);
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begin
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-- Global FPGA reset.
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-- GPIO(0) = '0' to reset.
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s_ext_reset_n <= s_gpio_out(0);
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-- GPIO inputs to the PS.
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-- GPIO(1) = '0' while in reset, '1' when reset released.
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s_gpio_in(1) <= r_reset_done;
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s_gpio_in(0) <= '0';
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s_gpio_in(23 downto 2) <= (others => '0');
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-- Drive LEDs.
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led_o(0) <= r_adcclk_led; -- blinking LED, 1 Hz
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led_o(1) <= s_reg_control.acquisition_en; -- acquisition enabled
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led_o(2) <= s_reg_status.trig_waiting; -- waiting for trigger
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led_o(3) <= or_reduce(s_reg_control.timetagger_en); -- timetagger enabled
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led_o(7 downto 4) <= s_reg_control.led_state(7 downto 4);
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-- Drive safe levels to unused DAC pins.
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dac_pwm_o <= (others => 'Z');
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-- Use extension I/O pins as inputs only.
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exp_p_io <= (others => 'Z');
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exp_n_io <= (others => 'Z');
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-- Drive SPI bus.
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inst_obuf_spi_clk: OBUFT
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port map (
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I => s_spi_sclk_o,
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T => s_spi_sclk_t,
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O => spi_clk_o );
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inst_obuf_spi_mosi: OBUFT
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port map (
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I => s_spi_mosi_o,
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T => s_spi_mosi_t,
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O => spi_mosi_o );
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inst_obuf_spi_csa: OBUFT
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port map (
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I => s_spi_ss_o(0),
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T => s_spi_ss_t,
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O => spi_csa_o );
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inst_obuf_spi_csb: OBUFT
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port map (
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I => s_spi_ss_o(1),
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T => s_spi_ss_t,
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O => spi_csb_o );
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-- Handle clock input and data input for each ADC.
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gen_adcin: for i in 0 to 1 generate
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-- Differential clock input for ADC clock.
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inst_ibuf_adc_clk: IBUFDS
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port map (
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O => s_adc_clk_ibuf(i),
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I => adc_clk_i(i)(1),
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IB => adc_clk_i(i)(0) );
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-- Clock buffer for ADC clock.
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-- BUFR is faster (lower propagation delay) than BUFG.
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inst_bufg_adc_clk: BUFR
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port map (
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I => s_adc_clk_ibuf(i),
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O => clk_adc_capture(i),
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CE => '1',
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CLR => '0' );
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end generate;
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-- PLL for 125 MHz clock.
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-- Input clock comes from ADC A.
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-- Output clock drives most of the FPGA design.
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inst_pll: PLLE2_BASE
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generic map (
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BANDWIDTH => "OPTIMIZED",
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CLKFBOUT_MULT => 8,
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CLKFBOUT_PHASE => 0.0,
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CLKIN1_PERIOD => 8.0,
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CLKOUT0_DIVIDE => 8,
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CLKOUT0_DUTY_CYCLE => 0.5,
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CLKOUT0_PHASE => 0.0,
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DIVCLK_DIVIDE => 1,
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STARTUP_WAIT => "FALSE" )
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port map (
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CLKOUT0 => s_pll_clkout,
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CLKFBOUT => s_pll_clkfbout,
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LOCKED => s_pll_locked,
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CLKIN1 => s_adc_clk_ibuf(0),
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PWRDWN => '0',
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RST => s_pll_reset,
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CLKFBIN => s_pll_clkfbin );
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-- Reset PLL when external reset is applied.
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s_pll_reset <= not s_ext_reset_n;
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-- Clock buffers for PLL.
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inst_bufg_pll_clkfb: BUFG
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port map (
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I => s_pll_clkfbout,
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O => s_pll_clkfbin );
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inst_bufg_pll_clkout: BUFG
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port map (
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I => s_pll_clkout,
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O => clk_adc );
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-- Since the design uses IDELAY, it must contain an IDELAYCTRL instance.
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inst_idelayctrl: IDELAYCTRL
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port map (
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RDY => open,
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REFCLK => clk_fclk200,
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RST => s_pll_reset );
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-- ARM/PS block design.
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inst_blockdesign: entity work.puzzlefw_wrapper
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port map (
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sys_clk => clk_adc,
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ps_fclk => clk_fclk200,
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peripheral_reset_0(0) => s_reset,
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ext_reset_in_0 => s_ext_reset_n,
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dcm_locked_0 => s_pll_locked,
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DDR_0_addr => DDR_0_addr,
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DDR_0_ba => DDR_0_ba,
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DDR_0_cas_n => DDR_0_cas_n,
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DDR_0_ck_n => DDR_0_ck_n,
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DDR_0_ck_p => DDR_0_ck_p,
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DDR_0_cke => DDR_0_cke,
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DDR_0_cs_n => DDR_0_cs_n,
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DDR_0_dm => DDR_0_dm,
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DDR_0_dq => DDR_0_dq,
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DDR_0_dqs_n => DDR_0_dqs_n,
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DDR_0_dqs_p => DDR_0_dqs_p,
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DDR_0_odt => DDR_0_odt,
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DDR_0_ras_n => DDR_0_ras_n,
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DDR_0_reset_n => DDR_0_reset_n,
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DDR_0_we_n => DDR_0_we_n,
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FIXED_IO_0_ddr_vrn => FIXED_IO_0_ddr_vrn,
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FIXED_IO_0_ddr_vrp => FIXED_IO_0_ddr_vrp,
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FIXED_IO_0_mio => FIXED_IO_0_mio,
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FIXED_IO_0_ps_clk => FIXED_IO_0_ps_clk,
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FIXED_IO_0_ps_porb => FIXED_IO_0_ps_porb,
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FIXED_IO_0_ps_srstb => FIXED_IO_0_ps_srstb,
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GPIO_I_0 => s_gpio_in,
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GPIO_O_0 => s_gpio_out,
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SPI0_MOSI_O_0 => s_spi_mosi_o,
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SPI0_MOSI_T_0 => s_spi_mosi_t,
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SPI0_SCLK_O_0 => s_spi_sclk_o,
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SPI0_SCLK_T_0 => s_spi_sclk_t,
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SPI0_SS1_O_0 => s_spi_ss_o(1),
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SPI0_SS_O_0 => s_spi_ss_o(0),
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SPI0_SS_T_0 => s_spi_ss_t,
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IRQ_F2P => s_irq_f2p,
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APB_M_0_paddr => s_apb_paddr,
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APB_M_0_penable => s_apb_penable,
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APB_M_0_prdata => s_apb_prdata,
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APB_M_0_pready(0) => s_apb_pready,
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APB_M_0_psel(0) => s_apb_psel,
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APB_M_0_pslverr(0) => s_apb_pslverr,
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APB_M_0_pwdata => s_apb_pwdata,
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APB_M_0_pwrite => s_apb_pwrite,
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S_AXI_HP0_0_araddr => s_axi_araddr,
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S_AXI_HP0_0_arburst => s_axi_arburst,
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S_AXI_HP0_0_arcache => s_axi_arcache,
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S_AXI_HP0_0_arid => s_axi_arid,
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S_AXI_HP0_0_arlen => s_axi_arlen,
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S_AXI_HP0_0_arlock => s_axi_arlock,
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S_AXI_HP0_0_arprot => s_axi_arprot,
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S_AXI_HP0_0_arqos => s_axi_arqos,
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S_AXI_HP0_0_arready => s_axi_arready,
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S_AXI_HP0_0_arsize => s_axi_arsize,
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S_AXI_HP0_0_arvalid => s_axi_arvalid,
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S_AXI_HP0_0_awaddr => s_axi_awaddr,
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S_AXI_HP0_0_awburst => s_axi_awburst,
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S_AXI_HP0_0_awcache => s_axi_awcache,
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S_AXI_HP0_0_awid => s_axi_awid,
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S_AXI_HP0_0_awlen => s_axi_awlen,
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S_AXI_HP0_0_awlock => s_axi_awlock,
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S_AXI_HP0_0_awprot => s_axi_awprot,
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S_AXI_HP0_0_awqos => s_axi_awqos,
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S_AXI_HP0_0_awready => s_axi_awready,
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S_AXI_HP0_0_awsize => s_axi_awsize,
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S_AXI_HP0_0_awvalid => s_axi_awvalid,
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S_AXI_HP0_0_bid => s_axi_bid,
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S_AXI_HP0_0_bready => s_axi_bready,
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S_AXI_HP0_0_bresp => s_axi_bresp,
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S_AXI_HP0_0_bvalid => s_axi_bvalid,
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S_AXI_HP0_0_rdata => s_axi_rdata,
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S_AXI_HP0_0_rid => s_axi_rid,
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S_AXI_HP0_0_rlast => s_axi_rlast,
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S_AXI_HP0_0_rready => s_axi_rready,
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S_AXI_HP0_0_rresp => s_axi_rresp,
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S_AXI_HP0_0_rvalid => s_axi_rvalid,
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S_AXI_HP0_0_wdata => s_axi_wdata,
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S_AXI_HP0_0_wid => s_axi_wid,
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S_AXI_HP0_0_wlast => s_axi_wlast,
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S_AXI_HP0_0_wready => s_axi_wready,
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S_AXI_HP0_0_wstrb => s_axi_wstrb,
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S_AXI_HP0_0_wvalid => s_axi_wvalid
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);
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-- Memory-mapped registers.
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inst_registers: entity work.registers
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generic map (
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num_acq_channels => 4 )
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port map (
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clk => clk_adc,
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reset => s_reset,
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apb_psel => s_apb_psel,
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apb_penable => s_apb_penable,
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apb_pwrite => s_apb_pwrite,
|
|
apb_paddr => s_apb_paddr,
|
|
apb_pwdata => s_apb_pwdata,
|
|
apb_pready => s_apb_pready,
|
|
apb_pslverr => s_apb_pslverr,
|
|
apb_prdata => s_apb_prdata,
|
|
reg_control => s_reg_control,
|
|
reg_status => s_reg_status
|
|
);
|
|
|
|
-- AXI master.
|
|
inst_axi_master: entity work.dma_axi_master
|
|
generic map (
|
|
num_read_channels => 0,
|
|
num_write_channels => 2 )
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
dma_en => s_reg_control.dma_en,
|
|
dma_busy => s_reg_status.dma_busy,
|
|
window_base_addr => s_reg_control.dma_buf_addr,
|
|
window_size => s_reg_control.dma_buf_size,
|
|
err_read => s_reg_status.dma_err_read,
|
|
err_write => s_reg_status.dma_err_write,
|
|
err_address => s_reg_status.dma_err_address,
|
|
err_any => s_reg_status.dma_err_any,
|
|
clear_errors => s_reg_control.dma_clear,
|
|
read_cmd_addr => (others => (others => '0')),
|
|
read_cmd_length => (others => (others => '0')),
|
|
read_cmd_valid => (others => '0'),
|
|
read_cmd_ready => open,
|
|
read_data => open,
|
|
read_data_valid => open,
|
|
write_cmd_addr => s_dma_write_cmd_addr,
|
|
write_cmd_length => s_dma_write_cmd_length,
|
|
write_cmd_valid => s_dma_write_cmd_valid,
|
|
write_cmd_ready => s_dma_write_cmd_ready,
|
|
write_data => s_dma_write_data,
|
|
write_data_ready => s_dma_write_data_ready,
|
|
write_finished => s_dma_write_finished,
|
|
m_axi_awid => s_axi_awid,
|
|
m_axi_awaddr => s_axi_awaddr,
|
|
m_axi_awlen => s_axi_awlen,
|
|
m_axi_awsize => s_axi_awsize,
|
|
m_axi_awburst => s_axi_awburst,
|
|
m_axi_awlock => s_axi_awlock,
|
|
m_axi_awcache => s_axi_awcache,
|
|
m_axi_awprot => s_axi_awprot,
|
|
m_axi_awqos => s_axi_awqos,
|
|
m_axi_awvalid => s_axi_awvalid,
|
|
m_axi_awready => s_axi_awready,
|
|
m_axi_wid => s_axi_wid,
|
|
m_axi_wdata => s_axi_wdata,
|
|
m_axi_wstrb => s_axi_wstrb,
|
|
m_axi_wlast => s_axi_wlast,
|
|
m_axi_wvalid => s_axi_wvalid,
|
|
m_axi_wready => s_axi_wready,
|
|
m_axi_bid => s_axi_bid,
|
|
m_axi_bresp => s_axi_bresp,
|
|
m_axi_bvalid => s_axi_bvalid,
|
|
m_axi_bready => s_axi_bready,
|
|
m_axi_arid => s_axi_arid,
|
|
m_axi_araddr => s_axi_araddr,
|
|
m_axi_arlen => s_axi_arlen,
|
|
m_axi_arsize => s_axi_arsize,
|
|
m_axi_arburst => s_axi_arburst,
|
|
m_axi_arlock => s_axi_arlock,
|
|
m_axi_arcache => s_axi_arcache,
|
|
m_axi_arprot => s_axi_arprot,
|
|
m_axi_arqos => s_axi_arqos,
|
|
m_axi_arvalid => s_axi_arvalid,
|
|
m_axi_arready => s_axi_arready,
|
|
m_axi_rid => s_axi_rid,
|
|
m_axi_rdata => s_axi_rdata,
|
|
m_axi_rresp => s_axi_rresp,
|
|
m_axi_rlast => s_axi_rlast,
|
|
m_axi_rvalid => s_axi_rvalid,
|
|
m_axi_rready => s_axi_rready
|
|
);
|
|
|
|
-- DMA write channel for analog acquisition
|
|
inst_acq_dma: entity work.dma_write_channel
|
|
generic map (
|
|
transfer_size_bits => 4,
|
|
queue_size_bits => 14,
|
|
idle_timeout => 256 )
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
channel_en => s_reg_control.acq_dma_en,
|
|
channel_busy => s_reg_status.acq_dma_busy,
|
|
channel_init => s_reg_control.acq_dma_init,
|
|
addr_start => s_reg_control.acq_addr_start,
|
|
addr_end => s_reg_control.acq_addr_end,
|
|
addr_limit => s_reg_control.acq_addr_limit,
|
|
addr_interrupt => s_reg_control.acq_addr_intr,
|
|
addr_pointer => s_reg_status.acq_addr_ptr,
|
|
intr_en => s_reg_control.acq_intr_en,
|
|
intr_clear => s_reg_control.acq_intr_clear,
|
|
intr_out => s_irq_pending(0),
|
|
in_valid => s_acq_dma_valid,
|
|
in_ready => s_acq_dma_ready,
|
|
in_empty => s_acq_dma_empty,
|
|
in_data => s_acq_dma_data,
|
|
write_cmd_addr => s_dma_write_cmd_addr(0),
|
|
write_cmd_length => s_dma_write_cmd_length(0),
|
|
write_cmd_valid => s_dma_write_cmd_valid(0),
|
|
write_cmd_ready => s_dma_write_cmd_ready(0),
|
|
write_data => s_dma_write_data(0),
|
|
write_data_ready => s_dma_write_data_ready(0),
|
|
write_finished => s_dma_write_finished(0) );
|
|
|
|
-- DMA write channel for time tagger
|
|
inst_tt_dma: entity work.dma_write_channel
|
|
generic map (
|
|
transfer_size_bits => 4,
|
|
queue_size_bits => 12,
|
|
idle_timeout => 256 )
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
channel_en => s_reg_control.tt_dma_en,
|
|
channel_busy => s_reg_status.tt_dma_busy,
|
|
channel_init => s_reg_control.tt_dma_init,
|
|
addr_start => s_reg_control.tt_addr_start,
|
|
addr_end => s_reg_control.tt_addr_end,
|
|
addr_limit => s_reg_control.tt_addr_limit,
|
|
addr_interrupt => s_reg_control.tt_addr_intr,
|
|
addr_pointer => s_reg_status.tt_addr_ptr,
|
|
intr_en => s_reg_control.tt_intr_en,
|
|
intr_clear => s_reg_control.tt_intr_clear,
|
|
intr_out => s_irq_pending(1),
|
|
in_valid => s_tt_dma_valid,
|
|
in_ready => s_tt_dma_ready,
|
|
in_empty => s_tt_dma_empty,
|
|
in_data => s_tt_dma_data,
|
|
write_cmd_addr => s_dma_write_cmd_addr(1),
|
|
write_cmd_length => s_dma_write_cmd_length(1),
|
|
write_cmd_valid => s_dma_write_cmd_valid(1),
|
|
write_cmd_ready => s_dma_write_cmd_ready(1),
|
|
write_data => s_dma_write_data(1),
|
|
write_data_ready => s_dma_write_data_ready(1),
|
|
write_finished => s_dma_write_finished(1) );
|
|
|
|
-- Timestamp generator.
|
|
inst_timestamp_gen: entity work.timestamp_gen
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
clear => s_reg_control.timestamp_clear,
|
|
timestamp => s_timestamp );
|
|
|
|
s_reg_status.timestamp <= s_timestamp;
|
|
|
|
-- Capture ADC data.
|
|
-- ADC A handles channels 0 and 1.
|
|
-- ADC B handles channels 2 and 3.
|
|
-- Each channel receives one 14-bit sample per clock cycle.
|
|
-- The 14 bits are transferred through 7 DDR signals.
|
|
gen_adc_capture: for i in 0 to 3 generate
|
|
inst_adc_capture: entity work.adc_capture_ddr
|
|
port map (
|
|
clk_capture => clk_adc_capture(i / 2),
|
|
clk_intermediate => clk_adc_capture(0),
|
|
clk_handoff => clk_adc,
|
|
in_data => adc_dat_i(i),
|
|
out_data => s_adc_data(i) );
|
|
end generate;
|
|
|
|
-- Optionally generate simulated ADC samples.
|
|
gen_adc_sample_stream: for i in 0 to 1 generate
|
|
inst_adc_sample_stream: entity work.adc_sample_stream
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
simulate => s_reg_control.simulate_adc,
|
|
in_data => s_adc_data(2*i to 2*i+1),
|
|
out_data => s_adc_sample(2*i to 2*i+1) );
|
|
end generate;
|
|
|
|
-- Monitor range of ADC samples.
|
|
inst_monitor_gen: for i in 0 to 3 generate
|
|
inst_range_monitor: entity work.adc_range_monitor
|
|
generic map (
|
|
signed_data => false )
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
clear => s_reg_control.adc_range_clear,
|
|
in_data => s_adc_sample(i),
|
|
min_value => s_reg_status.adc_min_value(i),
|
|
max_value => s_reg_status.adc_max_value(i) );
|
|
end generate;
|
|
|
|
-- Monitor current ADC sample value.
|
|
s_reg_status.adc_sample <= s_adc_sample;
|
|
|
|
-- Analog acquisition data chain.
|
|
inst_acquisition_chain: entity work.acquisition_chain
|
|
generic map (
|
|
num_channels => 4 )
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
acquisition_en => s_reg_control.acquisition_en,
|
|
trigger_delay => s_reg_control.trigger_delay,
|
|
record_length => s_reg_control.record_length,
|
|
decimation_factor => s_reg_control.decimation_factor,
|
|
averaging => s_reg_control.averaging_en,
|
|
shift_steps => s_reg_control.shift_steps,
|
|
ch4_mode => s_reg_control.ch4_mode,
|
|
trig_auto_en => s_reg_control.trig_auto_en,
|
|
trig_ext_en => s_reg_control.trig_ext_en,
|
|
trig_ext_once => s_reg_control.trig_ext_once,
|
|
trig_force => s_reg_control.trig_force,
|
|
trig_ext_select => s_reg_control.trig_ext_select,
|
|
trig_ext_falling => s_reg_control.trig_ext_falling,
|
|
timestamp_in => s_timestamp,
|
|
adc_data_in => s_adc_sample,
|
|
trig_ext_in => s_dig_sample,
|
|
trig_waiting => s_reg_status.trig_waiting,
|
|
trig_detected => s_reg_status.trig_detected,
|
|
out_valid => s_acq_dma_valid,
|
|
out_ready => s_acq_dma_ready,
|
|
out_empty => s_acq_dma_empty,
|
|
out_data => s_acq_dma_data );
|
|
|
|
-- Capture digital inputs.
|
|
s_dig_in(0) <= exp_p_io(0);
|
|
s_dig_in(1) <= exp_n_io(0);
|
|
s_dig_in(2) <= exp_p_io(1);
|
|
s_dig_in(3) <= exp_n_io(1);
|
|
|
|
inst_dig_capture_gen: for i in 0 to 3 generate
|
|
|
|
-- Use a 2-flipflop synchronizer to avoid metastability.
|
|
inst_dig_sync: entity work.syncdff
|
|
port map (
|
|
clk => clk_adc,
|
|
di => s_dig_in(i),
|
|
do => s_dig_sync(i) );
|
|
|
|
-- Deglitch filter.
|
|
inst_dig_deglitch: entity work.deglitch
|
|
generic map (
|
|
deglitch_cycles => 4 )
|
|
port map (
|
|
clk => clk_adc,
|
|
din => s_dig_sync(i),
|
|
dout => s_dig_deglitch(i) );
|
|
|
|
end generate;
|
|
|
|
-- Optionally generate simulated digital signals.
|
|
process (clk_adc) is
|
|
begin
|
|
if rising_edge(clk_adc) then
|
|
if s_reg_control.dig_simulate = '1' then
|
|
s_dig_sample <= s_reg_control.dig_sim_state;
|
|
else
|
|
s_dig_sample <= s_dig_deglitch;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
-- Monitor digital signal state.
|
|
s_reg_status.dig_sample <= s_dig_sample;
|
|
|
|
-- Time tagger.
|
|
inst_timetagger: entity work.timetagger
|
|
port map (
|
|
clk => clk_adc,
|
|
reset => s_reset,
|
|
channel_en => s_reg_control.timetagger_en,
|
|
marker => s_reg_control.timetagger_mark,
|
|
timestamp_in => s_timestamp,
|
|
dig_sample => s_dig_sample,
|
|
out_valid => s_tt_dma_valid,
|
|
out_ready => s_tt_dma_ready,
|
|
out_empty => s_tt_dma_empty,
|
|
out_data => s_tt_dma_data );
|
|
|
|
-- Collect interrupt signals from peripherals and generate interrupt to PS.
|
|
s_reg_status.irq_pending <= s_irq_pending;
|
|
s_irq_f2p(0) <= s_reg_control.irq_enable and or_reduce(s_irq_pending);
|
|
s_irq_f2p(7 downto 1) <= (others => '0');
|
|
|
|
-- Report reset status via GPIO.
|
|
process (clk_adc, s_ext_reset_n) is
|
|
begin
|
|
if s_ext_reset_n = '0' then
|
|
r_reset_done <= '0';
|
|
elsif rising_edge(clk_adc) then
|
|
r_reset_done <= not s_reset;
|
|
end if;
|
|
end process;
|
|
|
|
-- Blinking LED, 1 Hz.
|
|
process (clk_adc) is
|
|
begin
|
|
if rising_edge(clk_adc) then
|
|
if s_reset = '1' then
|
|
r_adcclk_cnt <= (others => '0');
|
|
r_adcclk_led <= '0';
|
|
elsif r_adcclk_cnt = 62499999 then
|
|
r_adcclk_cnt <= (others => '0');
|
|
r_adcclk_led <= not r_adcclk_led;
|
|
else
|
|
r_adcclk_cnt <= r_adcclk_cnt + 1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end architecture;
|