94 lines
1.9 KiB
VHDL
94 lines
1.9 KiB
VHDL
--
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-- Remove glitches from a digital signal.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity deglitch is
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generic (
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-- The output follows the input when the input is stable
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-- for "deglitch_cycles" clock cycles.
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--
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-- A glitch-free transition on the input, propagates to the output
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-- after a delay of "deglitch_cycles" clock cycles.
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--
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deglitch_cycles: integer range 2 to 16 := 4
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);
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Input signal.
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din: in std_logic;
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-- Deglitched output signal.
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dout: out std_logic
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);
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end entity;
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architecture arch of deglitch is
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type regs_type is record
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cnt: integer range 0 to deglitch_cycles - 1;
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dout: std_logic;
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end record;
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constant regs_init: regs_type := (
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cnt => 0,
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dout => '0'
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);
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signal r: regs_type := regs_init;
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signal rnext: regs_type;
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begin
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-- Drive output.
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dout <= r.dout;
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--
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-- Combinatorial process.
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--
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process (all) is
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variable v: regs_type;
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variable v_trig: std_logic;
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begin
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-- Load current register values.
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v := r;
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if (din xor r.dout) = '1' then
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if r.cnt = deglitch_cycles - 1 then
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v.dout := din;
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v.cnt := 0;
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else
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v.cnt := r.cnt + 1;
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end if;
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else
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v.cnt := 0;
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end if;
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-- Drive new register values to synchronous process.
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rnext <= v;
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end process;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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r <= rnext;
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end if;
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end process;
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end architecture;
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