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joris
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redpitaya-puzzlefw
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redpitaya-puzzlefw
/
fpga
/
vivado
/
redpitaya_puzzlefw.srcs
/
sources_1
/
bd
/
puzzlefw
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Joris van Rantwijk
4d79fecfdc
Change FCLK0 frequency to 200 MHz
...
This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
2024-10-06 12:58:11 +02:00
..
puzzlefw.bd
Change FCLK0 frequency to 200 MHz
2024-10-06 12:58:11 +02:00