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Disable Hierarchical synthesis of block design 

This is required for proper synthesis in non-project mode.
This commit is contained in:
Joris van Rantwijk 2024-08-03 12:25:59 +02:00
parent a5f4e25c76
commit 8d7f53e182
1 changed files with 1 additions and 1 deletions
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fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
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@ -6,7 +6,7 @@
"gen_directory": "../../../../redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw", "gen_directory": "../../../../redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw",
"name": "puzzlefw", "name": "puzzlefw",
"rev_ctrl_bd_flag": "RevCtrlBdOff", "rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical", "synth_flow_mode": "None",
"tool_version": "2020.2", "tool_version": "2020.2",
"validated": "true" "validated": "true"
}, },