Add register bit to show 4-channel support

Firmware version 0.8.

doc/fpga_firmware.md

@@ -549,6 +549,7 @@ Enable 4-channel sampling (only supported on 4-channel devices).
 | Bits    | Field name    | Access | Description |
 |---------|---------------|--------|-------------|
 | 0       | ch4_mode      | RW     | '1' to enable 4-channel sampling. |
+| 8       | ch4_enabled   | RO     | '1' for a 4-channel device. |
 
 When 4-channel sampling is disabled, only channels IN1 and IN2 are active.
 One 64-bit word is emitted for each decimated sample, containing the data of these two channels.

fpga/rtl/puzzlefw_pkg.vhd

@@ -94,7 +94,7 @@ package puzzlefw_pkg is
     -- Firmware info word.
     constant fw_api_version:        natural := 1;
     constant fw_version_major:      natural := 0;
-    constant fw_version_minor:      natural := 7;
+    constant fw_version_minor:      natural := 8;
     constant fw_info_word:          std_logic_vector(31 downto 0) :=
         x"4a"
         & std_logic_vector(to_unsigned(fw_api_version, 8))

fpga/rtl/puzzlefw_top.vhd

@@ -286,6 +286,8 @@ begin
 
     -- Memory-mapped registers.
     inst_registers: entity work.registers
+        generic map (
+            num_acq_channels    => 2 )
         port map (
             clk                 => clk_adc,
             reset               => s_reset,

fpga/rtl/registers.vhd

@@ -13,6 +13,11 @@ use work.puzzlefw_pkg.all;
 
 entity registers is
 
+    generic (
+        -- Number of analog input channels. It should be either 2 or 4.
+        num_acq_channels:   integer range 2 to 4
+    );
+
     port (
         -- Main clock, active on rising edge.
         clk:                in  std_logic;
@@ -116,7 +121,11 @@ begin
                 when reg_decimation_factor => v.prdata(17 downto 0) := r.reg_control.decimation_factor;
                 when reg_shift_steps =>     v.prdata(3 downto 0) := r.reg_control.shift_steps;
                 when reg_averaging_en =>    v.prdata(0) := r.reg_control.averaging_en;
-                when reg_ch4_mode =>        v.prdata(0) := r.reg_control.ch4_mode;
+                when reg_ch4_mode =>
+                    v.prdata(0) := r.reg_control.ch4_mode;
+                    if num_acq_channels > 2 then
+                        v.prdata(8) := '1';
+                    end if;
                 when reg_simulate_adc =>    v.prdata(0) := r.reg_control.simulate_adc;
                 when reg_trigger_mode =>
                     v.prdata(0) := r.reg_control.trig_auto_en;
@@ -186,7 +195,10 @@ begin
                 when reg_decimation_factor => v.reg_control.decimation_factor := apb_pwdata(17 downto 0);
                 when reg_shift_steps =>     v.reg_control.shift_steps := apb_pwdata(3 downto 0);
                 when reg_averaging_en =>    v.reg_control.averaging_en := apb_pwdata(0);
-                when reg_ch4_mode =>        v.reg_control.ch4_mode := apb_pwdata(0);
+                when reg_ch4_mode =>
+                    if num_acq_channels > 2 then
+                        v.reg_control.ch4_mode := apb_pwdata(0);
+                    end if;
                 when reg_simulate_adc =>    v.reg_control.simulate_adc := apb_pwdata(0);
                 when reg_trigger_mode =>
                     v.reg_control.trig_auto_en := apb_pwdata(0);