Add monitoring of ADC sample and min/max range
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716d16e6a3
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@ -54,9 +54,6 @@ entity acquisition_chain is
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-- Ignored if num_channels == 2.
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ch4_mode: in std_logic;
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-- High to use simulated samples in place of real ADC samples.
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simulate_adc: in std_logic;
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-- High to enable automatic (continuous) triggering.
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trig_auto_en: in std_logic;
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@ -142,25 +139,6 @@ begin
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sample_integrate => s_sample_integrate,
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sample_done => s_sample_done );
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-- Optionally generate simulated ADC data.
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inst_adc_sample_stream: entity work.adc_sample_stream
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port map (
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clk => clk,
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reset => reset,
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simulate => simulate_adc,
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in_data => adc_data_in(0 to 1),
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out_data => s_adc_sample(0 to 1) );
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inst_adc_sample_stream_gen: if num_channels > 2 generate
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inst_adc_sample_stream2: entity work.adc_sample_stream
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port map (
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clk => clk,
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reset => reset,
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simulate => simulate_adc,
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in_data => adc_data_in(2 to 3),
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out_data => s_adc_sample(2 to 3) );
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end generate;
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-- Shift and decimation chains for each ADC channel.
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inst_channels: for i in 0 to num_channels - 1 generate
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@ -172,7 +150,7 @@ begin
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signed_data => false )
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port map (
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clk => clk,
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in_data => s_adc_sample(i),
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in_data => adc_data_in(i),
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in_shift => shift_steps,
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out_data => s_adc_shifted(i) );
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@ -0,0 +1,107 @@
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--
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-- Monitor min/max sample values from ADC.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity adc_range_monitor is
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generic (
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-- True if ADC samples are signed values.
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-- False if ADC samples are unsigned binary offset values.
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signed_data: boolean
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);
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to clear min/max sample values.
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clear: in std_logic;
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-- Input sample stream.
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in_data: in adc_data_type;
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-- Minimum and maximum sample value observed.
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min_value: out adc_data_type;
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max_value: out adc_data_type
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);
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end entity;
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architecture arch of adc_range_monitor is
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type regs_type is record
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min_value: adc_data_type;
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max_value: adc_data_type;
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end record;
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signal r: regs_type;
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signal rnext: regs_type;
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-- Return True if X is less than Y.
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function sample_less(x: adc_data_type; y: adc_data_type)
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return boolean
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is begin
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if signed_data then
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return signed(x) < signed(y);
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else
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return unsigned(x) < unsigned(y);
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end if;
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end function;
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begin
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-- Drive output.
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min_value <= r.min_value;
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max_value <= r.max_value;
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--
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-- Combinatorial process.
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--
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process (all) is
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variable v: regs_type;
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begin
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-- Load current register values.
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v := r;
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-- Update min value.
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if (reset = '1')
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or (clear = '1')
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or sample_less(in_data, r.min_value) then
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v.min_value := in_data;
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end if;
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-- Update max value.
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if (reset = '1')
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or (clear = '1')
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or sample_less(r.max_value, in_data) then
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v.max_value := in_data;
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end if;
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-- Drive new register values to synchronous process.
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rnext <= v;
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end process;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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r <= rnext;
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end if;
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end process;
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end architecture;
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@ -67,6 +67,13 @@ package puzzlefw_pkg is
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constant reg_trigger_mode: natural := 16#000240#;
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constant reg_trigger_delay: natural := 16#000244#;
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constant reg_trigger_status: natural := 16#000248#;
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constant reg_adc_sample: natural := 16#000280#;
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constant reg_adc23_sample: natural := 16#000284#;
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constant reg_adc_range_clear: natural := 16#00028c#;
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constant reg_adc0_minmax: natural := 16#000290#;
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constant reg_adc1_minmax: natural := 16#000294#;
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constant reg_adc2_minmax: natural := 16#000298#;
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constant reg_adc3_minmax: natural := 16#00029c#;
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constant reg_test_led: natural := 16#000404#;
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constant reg_test_divider: natural := 16#000408#;
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constant reg_dma_buf_addr: natural := 16#100000#;
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@ -75,7 +82,7 @@ package puzzlefw_pkg is
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-- Firmware info word.
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constant fw_api_version: natural := 1;
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constant fw_version_major: natural := 0;
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constant fw_version_minor: natural := 3;
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constant fw_version_minor: natural := 4;
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constant fw_info_word: std_logic_vector(31 downto 0) :=
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x"4a"
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& std_logic_vector(to_unsigned(fw_api_version, 8))
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@ -116,6 +123,7 @@ package puzzlefw_pkg is
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trig_ext_select: std_logic_vector(1 downto 0);
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trig_ext_falling: std_logic;
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trigger_delay: std_logic_vector(15 downto 0);
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adc_range_clear: std_logic;
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dma_buf_addr: std_logic_vector(31 downto 12);
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dma_buf_size: std_logic_vector(31 downto 12);
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end record;
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@ -132,6 +140,9 @@ package puzzlefw_pkg is
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acq_addr_ptr: std_logic_vector(31 downto 3);
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acq_channel_busy: std_logic;
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trig_waiting: std_logic;
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adc_sample: adc_data_array(0 to 3);
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adc_min_value: adc_data_array(0 to 3);
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adc_max_value: adc_data_array(0 to 3);
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end record;
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constant registers_control_init: registers_control := (
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@ -162,6 +173,7 @@ package puzzlefw_pkg is
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trig_ext_select => (others => '0'),
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trig_ext_falling => '0',
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trigger_delay => (others => '0'),
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adc_range_clear => '0',
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dma_buf_addr => (others => '0'),
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dma_buf_size => (others => '0')
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);
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@ -136,21 +136,22 @@ architecture arch of puzzlefw_top is
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signal s_reg_control: registers_control;
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signal s_reg_status: registers_status;
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signal s_dma_write_cmd_addr: dma_address_array(0 downto 0);
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signal s_dma_write_cmd_length: dma_burst_length_array(0 to 0);
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signal s_dma_write_cmd_valid: std_logic_vector(0 downto 0);
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signal s_dma_write_cmd_ready: std_logic_vector(0 downto 0);
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signal s_dma_write_data: dma_data_array(0 downto 0);
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signal s_dma_write_data_ready: std_logic_vector(0 downto 0);
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signal s_dma_write_finished: std_logic_vector(0 downto 0);
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signal s_dma_write_cmd_addr: dma_address_array(0 downto 0);
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signal s_dma_write_cmd_length: dma_burst_length_array(0 to 0);
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signal s_dma_write_cmd_valid: std_logic_vector(0 downto 0);
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signal s_dma_write_cmd_ready: std_logic_vector(0 downto 0);
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signal s_dma_write_data: dma_data_array(0 downto 0);
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signal s_dma_write_data_ready: std_logic_vector(0 downto 0);
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signal s_dma_write_finished: std_logic_vector(0 downto 0);
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signal s_timestamp: std_logic_vector(timestamp_bits - 1 downto 0);
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signal s_adc_data: adc_data_array(0 to 1);
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signal s_adc_sample: adc_data_array(0 to 1);
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signal s_acq_dma_valid: std_logic;
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signal s_acq_dma_ready: std_logic;
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signal s_acq_dma_empty: std_logic;
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signal s_acq_dma_data: dma_data_type;
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signal s_acq_dma_valid: std_logic;
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signal s_acq_dma_ready: std_logic;
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signal s_acq_dma_empty: std_logic;
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signal s_acq_dma_data: dma_data_type;
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signal r_test_prefetch: std_logic;
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signal r_test_raddr: std_logic_vector(9 downto 0);
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@ -397,17 +398,44 @@ begin
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-- Capture ADC data.
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-- Ignore the 2 LSB bits which are not-connected on the ADC side.
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inst_adc_capture1: entity work.adc_capture
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port map (
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clk => clk_adc,
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in_data => adc_dat_i(0)(15 downto 2),
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out_data => s_adc_data(0) );
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inst_capture_gen: for i in 0 to 1 generate
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inst_adc_capture: entity work.adc_capture
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port map (
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clk => clk_adc,
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in_data => adc_dat_i(i)(15 downto 2),
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out_data => s_adc_data(i) );
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end generate;
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inst_adc_capture2: entity work.adc_capture
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-- Optionally generate simulated ADC samples.
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inst_adc_sample_stream: entity work.adc_sample_stream
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port map (
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clk => clk_adc,
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in_data => adc_dat_i(1)(15 downto 2),
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out_data => s_adc_data(1) );
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reset => s_reset,
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simulate => s_reg_control.simulate_adc,
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in_data => s_adc_data(0 to 1),
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out_data => s_adc_sample(0 to 1) );
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-- Monitor range of ADC samples.
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inst_monitor_gen: for i in 0 to 1 generate
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inst_range_monitor: entity work.adc_range_monitor
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generic map (
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signed_data => false )
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port map (
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clk => clk_adc,
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reset => s_reset,
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clear => s_reg_control.adc_range_clear,
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in_data => s_adc_sample(i),
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min_value => s_reg_status.adc_min_value(i),
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max_value => s_reg_status.adc_max_value(i) );
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end generate;
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-- Monitor current ADC sample value.
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s_reg_status.adc_sample(0 to 1) <= s_adc_sample(0 to 1);
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-- Drive dummy values to not-implemented channels 2, 3.
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s_reg_status.adc_sample(2 to 3) <= (others => (others => '0'));
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s_reg_status.adc_min_value(2 to 3) <= (others => (others => '0'));
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s_reg_status.adc_max_value(2 to 3) <= (others => (others => '0'));
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-- Analog acquisition data chain.
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inst_acquisition_chain: entity work.acquisition_chain
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@ -423,14 +451,13 @@ begin
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averaging => s_reg_control.averaging_en,
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shift_steps => s_reg_control.shift_steps,
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ch4_mode => s_reg_control.ch4_mode,
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simulate_adc => s_reg_control.simulate_adc,
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trig_auto_en => s_reg_control.trig_auto_en,
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trig_ext_en => s_reg_control.trig_ext_en,
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trig_force => s_reg_control.trig_force,
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trig_ext_select => s_reg_control.trig_ext_select,
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trig_ext_falling => s_reg_control.trig_ext_falling,
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timestamp_in => s_timestamp,
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adc_data_in => s_adc_data,
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adc_data_in => s_adc_sample,
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trig_ext_in => "0000", -- TODO
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trig_waiting => s_reg_status.trig_waiting,
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out_valid => s_acq_dma_valid,
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@ -75,6 +75,7 @@ begin
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v.reg_control.acq_channel_init := '0';
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v.reg_control.acq_intr_clear := '0';
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v.reg_control.trig_force := '0';
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v.reg_control.adc_range_clear := '0';
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-- Respond to each APB access on the next clock cycle (no wait states).
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v.pready := apb_psel and (not apb_penable);
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@ -122,6 +123,24 @@ begin
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v.prdata(7) := r.reg_control.trig_ext_falling;
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when reg_trigger_delay => v.prdata(15 downto 0) := r.reg_control.trigger_delay;
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when reg_trigger_status => v.prdata(0) := reg_status.trig_waiting;
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when reg_adc_sample =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_sample(0);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_sample(1);
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when reg_adc23_sample =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_sample(2);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_sample(3);
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when reg_adc0_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(0);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(0);
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when reg_adc1_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(1);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(1);
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when reg_adc2_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(2);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(2);
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when reg_adc3_minmax =>
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v.prdata(adc_data_bits - 1 downto 0) := reg_status.adc_min_value(3);
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v.prdata(adc_data_bits + 15 downto 16) := reg_status.adc_max_value(3);
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when reg_test_led => v.prdata(7 downto 0) := r.reg_control.test_led;
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when reg_test_divider => v.prdata(15 downto 0) := r.reg_control.test_divider;
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when reg_dma_buf_addr => v.prdata(31 downto 12) := r.reg_control.dma_buf_addr;
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@ -162,6 +181,7 @@ begin
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v.reg_control.trig_ext_falling := apb_pwdata(7);
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v.reg_control.trig_force := apb_pwdata(8);
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when reg_trigger_delay => v.reg_control.trigger_delay := apb_pwdata(15 downto 0);
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when reg_adc_range_clear => v.reg_control.adc_range_clear := apb_pwdata(0);
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when reg_test_led => v.reg_control.test_led := apb_pwdata(7 downto 0);
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when reg_test_divider => v.reg_control.test_divider := apb_pwdata(15 downto 0);
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when reg_dma_buf_addr => v.reg_control.dma_buf_addr := apb_pwdata(31 downto 12);
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@ -52,13 +52,7 @@ architecture arch of trigger_detector is
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trig_out: std_logic;
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end record;
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constant regs_init: regs_type := (
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prev_level => '0',
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ext_trig => '0',
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trig_out => '0'
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);
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signal r: regs_type := regs_init;
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signal r: regs_type;
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signal rnext: regs_type;
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begin
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@ -71,7 +65,6 @@ begin
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--
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process (all) is
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variable v: regs_type;
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variable v_trig: std_logic;
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begin
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-- Load current register values.
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v := r;
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@ -23,6 +23,7 @@ read_vhdl -vhdl2008 ../rtl/acquisition_chain.vhd
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read_vhdl -vhdl2008 ../rtl/acquisition_manager.vhd
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read_vhdl -vhdl2008 ../rtl/acquisition_stream.vhd
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read_vhdl -vhdl2008 ../rtl/adc_capture.vhd
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read_vhdl -vhdl2008 ../rtl/adc_range_monitor.vhd
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read_vhdl -vhdl2008 ../rtl/adc_sample_stream.vhd
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read_vhdl -vhdl2008 ../rtl/dma_axi_master.vhd
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read_vhdl -vhdl2008 ../rtl/dma_write_channel.vhd
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@ -51,6 +51,13 @@
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#define REG_TRIGGER_MODE 0x0240
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#define REG_TRIGGER_DELAY 0x0244
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#define REG_TRIGGER_STATUS 0x0248
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#define REG_ADC_SAMPLE 0x0280
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#define REG_ADC23_SAMPLE 0x0284
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#define REG_ADC_RANGE_CLEAR 0x028c
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#define REG_ADC0_MINMAX 0x0290
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#define REG_ADC1_MINMAX 0x0294
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#define REG_ADC2_MINMAX 0x0298
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#define REG_ADC3_MINMAX 0x029c
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struct puzzlefw_context {
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@ -601,6 +608,19 @@ static void show_status(struct puzzlefw_context *ctx)
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v = puzzlefw_read_reg(ctx, REG_AVERAGING_EN);
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printf(" averaging_en = 0x%08x\n", v);
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v = puzzlefw_read_reg(ctx, REG_ADC_SAMPLE);
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uint32_t adc_range = puzzlefw_read_reg(ctx, REG_ADC0_MINMAX);
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printf(" channel 0 = %5u (min = %u, max = %u)\n",
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v & 0xffff,
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adc_range & 0xffff,
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(adc_range >> 16) & 0xffff);
|
||||
|
||||
adc_range = puzzlefw_read_reg(ctx, REG_ADC1_MINMAX);
|
||||
printf(" channel 1 = %5u (min = %u, max = %u)\n",
|
||||
(v >> 16) & 0xffff,
|
||||
adc_range & 0xffff,
|
||||
(adc_range >> 16) & 0xffff);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1037,6 +1057,7 @@ int main(int argc, char **argv)
|
|||
int set_shift = 0, shift_steps = 0;
|
||||
int avgon = 0, avgoff = 0;
|
||||
int simon = 0, simoff = 0;
|
||||
int rangeclear = 0;
|
||||
|
||||
if (argc == 2 && strcmp(argv[1], "show") == 0) {
|
||||
show = 1;
|
||||
|
|
@ -1084,6 +1105,8 @@ int main(int argc, char **argv)
|
|||
simon = 1;
|
||||
} else if (argc == 2 && strcmp(argv[1], "simoff") == 0) {
|
||||
simoff = 1;
|
||||
} else if (argc == 2 && strcmp(argv[1], "rangeclear") == 0) {
|
||||
rangeclear = 1;
|
||||
} else if (argc == 2 && strcmp(argv[1], "server") == 0) {
|
||||
server = 1;
|
||||
} else {
|
||||
|
|
@ -1152,6 +1175,9 @@ int main(int argc, char **argv)
|
|||
" testje simoff\n"
|
||||
" Use real ADC data.\n"
|
||||
"\n"
|
||||
" testje rangeclear\n"
|
||||
" Clear min/max ADC sample monitor.\n"
|
||||
"\n"
|
||||
" testje server\n"
|
||||
" Open TCP port 5001 to stream DMA data.\n"
|
||||
"\n");
|
||||
|
|
@ -1251,6 +1277,10 @@ int main(int argc, char **argv)
|
|||
puzzlefw_write_reg(&ctx, REG_SIMULATE_ADC, 0);
|
||||
}
|
||||
|
||||
if (rangeclear) {
|
||||
puzzlefw_write_reg(&ctx, REG_ADC_RANGE_CLEAR, 1);
|
||||
}
|
||||
|
||||
if (server) {
|
||||
run_server(&ctx);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue