redpitaya-puzzlefw/fpga/rtl/deglitch.vhd

--
--  Remove glitches from a digital signal.
--
--  Joris van Rantwijk 2024
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity deglitch is

    generic (
        -- The output follows the input when the input is stable
        -- for "deglitch_cycles" clock cycles.
        --
        -- A glitch-free transition on the input, propagates to the output
        -- after a delay of "deglitch_cycles" clock cycles.
        --
        deglitch_cycles:    integer range 2 to 16 := 4
    );

    port (
        -- Main clock, active on rising edge.
        clk:                in  std_logic;

        -- Input signal.
        din:                in  std_logic;

        -- Deglitched output signal.
        dout:               out std_logic
    );

end entity;

architecture arch of deglitch is

    type regs_type is record
        cnt:            integer range 0 to deglitch_cycles - 1;
        dout:           std_logic;
    end record;

    constant regs_init: regs_type := (
        cnt             => 0,
        dout            => '0'
    );

    signal r: regs_type := regs_init;
    signal rnext: regs_type;

begin

    -- Drive output.
    dout <= r.dout;

    --
    -- Combinatorial process.
    --
    process (all) is
        variable v: regs_type;
        variable v_trig: std_logic;
    begin
        -- Load current register values.
        v := r;

        if (din xor r.dout) = '1' then
            if r.cnt = deglitch_cycles - 1 then
                v.dout := din;
                v.cnt  := 0;
            else
                v.cnt := r.cnt + 1;
            end if;
        else
            v.cnt := 0;
        end if;

        -- Drive new register values to synchronous process.
        rnext <= v;
    
    end process;

    --
    -- Synchronous process.
    --
    process (clk) is
    begin
        if rising_edge(clk) then
            r <= rnext;
        end if;
    end process;

end architecture;