81 lines
2.1 KiB
VHDL
81 lines
2.1 KiB
VHDL
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--
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-- Manage the ADC sample stream.
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--
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-- Optionally generates simulated samples in place of real ADC data.
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-- The simulated sample stream works as follows:
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-- - Both simulated channels output a simple increasing ramp.
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-- - The output of channel 0 increments at a rate of 1 per clock cycle.
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-- - The output of channel 1 increments by 1 whenever channel 0 wraps around.
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--
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-- This entity adds 1 clock cycle delay in the ADC sample stream.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity adc_sample_stream is
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to select simulated samples in place of ADC data.
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simulate: in std_logic;
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-- Input sample stream from ADC.
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in_data: in adc_data_array(0 to 1);
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-- Output sample stream.
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out_data: out adc_data_array(0 to 1)
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);
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end entity;
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architecture arch of adc_sample_stream is
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signal r_counter: unsigned(2 * adc_data_bits - 1 downto 0);
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signal r_out_data: adc_data_array(0 to 1);
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begin
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-- Drive output ports.
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out_data <= r_out_data;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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-- Select ADC sample or simulated sample.
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if simulate = '1' then
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-- Output simulated sample.
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r_out_data(0) <= std_logic_vector(r_counter(adc_data_bits - 1 downto 0));
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r_out_data(1) <= std_logic_vector(r_counter(2 * adc_data_bits - 1 downto adc_data_bits));
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else
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-- Output real ADC sample.
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r_out_data <= in_data;
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end if;
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-- Update simulated sample stream.
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if reset = '1' then
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r_counter <= (others => '0');
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else
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r_counter <= r_counter + 1;
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end if;
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end if;
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end process;
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end architecture;
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