441 lines
18 KiB
VHDL
441 lines
18 KiB
VHDL
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--
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-- Top-level FPGA design for Red Pitaya PuzzleFW firmware.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library xpm;
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use xpm.vcomponents.all;
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use work.puzzlefw_pkg.all;
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entity puzzlefw_top is
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port (
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-- Ports directly connected to ARM/PS.
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DDR_0_addr: inout std_logic_vector(14 downto 0);
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DDR_0_ba: inout std_logic_vector(2 downto 0);
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DDR_0_cas_n: inout std_logic;
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DDR_0_ck_n: inout std_logic;
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DDR_0_ck_p: inout std_logic;
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DDR_0_cke: inout std_logic;
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DDR_0_cs_n: inout std_logic;
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DDR_0_dm: inout std_logic_vector(3 downto 0);
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DDR_0_dq: inout std_logic_vector(31 downto 0);
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DDR_0_dqs_n: inout std_logic_vector(3 downto 0);
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DDR_0_dqs_p: inout std_logic_vector(3 downto 0);
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DDR_0_odt: inout std_logic;
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DDR_0_ras_n: inout std_logic;
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DDR_0_reset_n: inout std_logic;
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DDR_0_we_n: inout std_logic;
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FIXED_IO_0_ddr_vrn: inout std_logic;
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FIXED_IO_0_ddr_vrp: inout std_logic;
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FIXED_IO_0_mio: inout std_logic_vector(53 downto 0);
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FIXED_IO_0_ps_clk: inout std_logic;
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FIXED_IO_0_ps_porb: inout std_logic;
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FIXED_IO_0_ps_srstb: inout std_logic;
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-- Ports controlled by FPGA.
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adc_dat_i: in adc_data_input_type; -- ADC data
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adc_clk_i: in std_logic_vector(1 downto 0); -- ADC clock 1=pos, 0=neg
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adc_clk_o: out std_logic_vector(1 downto 0); -- optional clock output for ADC
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adc_cdcs_o: out std_logic; -- ADC clock duty cycle stabilizer
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dac_dat_o: out std_logic_vector(13 downto 0); -- DAC data
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dac_wrt_o: out std_logic; -- DAC write control
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dac_sel_o: out std_logic; -- DAC channel select
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dac_clk_o: out std_logic; -- DAC clock
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dac_rst_o: out std_logic; -- DAC reset
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dac_pwm_o: out std_logic_vector(3 downto 0); -- PWM DAC
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exp_p_io: inout std_logic_vector(7 downto 0); -- extension I/O pos
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exp_n_io: inout std_logic_vector(7 downto 0); -- extension I/O neg
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led_o: inout std_logic_vector(7 downto 0) -- LEDs
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);
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end puzzlefw_top;
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architecture arch of puzzlefw_top is
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-- Main 125 MHz clock, derived from ADC clock input port.
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signal clk_adc: std_logic;
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-- Auxiliary clock from FCLK0.
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signal clk_fclk: std_logic;
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-- Main reset signal, derived from FCLK_RESET0, active high, synchronous to clk_adc.
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signal s_reset: std_logic;
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signal s_adc_clk_ibuf: std_logic;
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signal r_fclk_cnt: unsigned(26 downto 0);
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signal r_fclk_led: std_logic;
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signal r_adcclk_cnt: unsigned(26 downto 0);
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signal r_adcclk_led: std_logic;
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signal s_apb_paddr: std_logic_vector(31 downto 0);
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signal s_apb_penable: std_logic;
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signal s_apb_prdata: std_logic_vector(31 downto 0);
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signal s_apb_pready: std_logic;
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signal s_apb_psel: std_logic;
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signal s_apb_pslverr: std_logic;
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signal s_apb_pwdata: std_logic_vector(31 downto 0);
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signal s_apb_pwrite: std_logic;
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signal s_axi_awid: std_logic_vector(5 downto 0);
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signal s_axi_awaddr: std_logic_vector(31 downto 0);
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signal s_axi_awlen: std_logic_vector(3 downto 0);
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signal s_axi_awsize: std_logic_vector(2 downto 0);
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signal s_axi_awburst: std_logic_vector(1 downto 0);
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signal s_axi_awlock: std_logic_vector(1 downto 0);
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signal s_axi_awcache: std_logic_vector(3 downto 0);
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signal s_axi_awprot: std_logic_vector(2 downto 0);
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signal s_axi_awqos: std_logic_vector(3 downto 0);
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signal s_axi_awvalid: std_logic;
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signal s_axi_awready: std_logic;
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signal s_axi_wid: std_logic_vector(5 downto 0);
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signal s_axi_wdata: std_logic_vector(63 downto 0);
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signal s_axi_wstrb: std_logic_vector(7 downto 0);
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signal s_axi_wlast: std_logic;
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signal s_axi_wvalid: std_logic;
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signal s_axi_wready: std_logic;
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signal s_axi_bid: std_logic_vector(5 downto 0);
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signal s_axi_bresp: std_logic_vector(1 downto 0);
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signal s_axi_bvalid: std_logic;
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signal s_axi_bready: std_logic;
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signal s_axi_arid: std_logic_vector(5 downto 0);
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signal s_axi_araddr: std_logic_vector(31 downto 0);
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signal s_axi_arlen: std_logic_vector(3 downto 0);
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signal s_axi_arsize: std_logic_vector(2 downto 0);
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signal s_axi_arburst: std_logic_vector(1 downto 0);
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signal s_axi_arlock: std_logic_vector(1 downto 0);
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signal s_axi_arcache: std_logic_vector(3 downto 0);
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signal s_axi_arprot: std_logic_vector(2 downto 0);
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signal s_axi_arqos: std_logic_vector(3 downto 0);
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signal s_axi_arvalid: std_logic;
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signal s_axi_arready: std_logic;
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signal s_axi_rid: std_logic_vector(5 downto 0);
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signal s_axi_rdata: std_logic_vector(63 downto 0);
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signal s_axi_rresp: std_logic_vector(1 downto 0);
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signal s_axi_rlast: std_logic;
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signal s_axi_rvalid: std_logic;
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signal s_axi_rready: std_logic;
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signal s_irq: std_logic_vector(7 downto 0);
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signal s_reg_control: registers_control;
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signal s_reg_status: registers_status;
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signal s_reg_trigger: registers_trigger;
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signal s_dma_read_cmd_addr: dma_address_type;
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signal s_dma_read_cmd_valid: std_logic;
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signal s_dma_read_cmd_ready: std_logic;
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signal s_dma_read_data: dma_data_type;
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signal s_dma_read_data_valid: std_logic;
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signal s_dma_write_cmd_addr: dma_address_type;
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signal s_dma_write_cmd_valid: std_logic;
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signal s_dma_write_cmd_ready: std_logic;
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signal s_dma_write_data: dma_data_type;
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signal s_dma_write_data_ready: std_logic;
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signal s_dma_write_finished: std_logic;
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signal r_test_prefetch: std_logic;
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signal r_test_raddr: std_logic_vector(9 downto 0);
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signal r_test_waddr: std_logic_vector(9 downto 0);
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signal s_test_dout: std_logic_vector(63 downto 0);
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signal s_test_ren: std_logic;
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begin
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s_irq <= s_reg_control.test_irq;
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led_o(7 downto 2) <= s_reg_control.test_led(7 downto 2);
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-- Differential clock input for ADC clock.
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inst_ibuf_adc_clk: IBUFDS
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port map (
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O => s_adc_clk_ibuf,
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I => adc_clk_i(1),
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IB => adc_clk_i(0)
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);
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-- Clock buffer for ADC clock.
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inst_bufg_adc_clk: BUFG
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port map (
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I => s_adc_clk_ibuf,
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O => clk_adc
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);
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inst_obuf_led0: OBUF
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port map (
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I => r_fclk_led,
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O => led_o(0)
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);
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inst_obuf_led1: OBUF
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port map (
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I => r_adcclk_led,
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O => led_o(1)
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);
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-- ARM/PS block design.
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inst_blockdesign: entity work.puzzlefw_wrapper
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port map (
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sys_clk => clk_adc,
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ps_fclk => clk_fclk,
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peripheral_reset_0(0) => s_reset,
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DDR_0_addr => DDR_0_addr,
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DDR_0_ba => DDR_0_ba,
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DDR_0_cas_n => DDR_0_cas_n,
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DDR_0_ck_n => DDR_0_ck_n,
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DDR_0_ck_p => DDR_0_ck_p,
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DDR_0_cke => DDR_0_cke,
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DDR_0_cs_n => DDR_0_cs_n,
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DDR_0_dm => DDR_0_dm,
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DDR_0_dq => DDR_0_dq,
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DDR_0_dqs_n => DDR_0_dqs_n,
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DDR_0_dqs_p => DDR_0_dqs_p,
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DDR_0_odt => DDR_0_odt,
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DDR_0_ras_n => DDR_0_ras_n,
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DDR_0_reset_n => DDR_0_reset_n,
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DDR_0_we_n => DDR_0_we_n,
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FIXED_IO_0_ddr_vrn => FIXED_IO_0_ddr_vrn,
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FIXED_IO_0_ddr_vrp => FIXED_IO_0_ddr_vrp,
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FIXED_IO_0_mio => FIXED_IO_0_mio,
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FIXED_IO_0_ps_clk => FIXED_IO_0_ps_clk,
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FIXED_IO_0_ps_porb => FIXED_IO_0_ps_porb,
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FIXED_IO_0_ps_srstb => FIXED_IO_0_ps_srstb,
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APB_M_0_paddr => s_apb_paddr,
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APB_M_0_penable => s_apb_penable,
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APB_M_0_prdata => s_apb_prdata,
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APB_M_0_pready(0) => s_apb_pready,
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APB_M_0_psel(0) => s_apb_psel,
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APB_M_0_pslverr(0) => s_apb_pslverr,
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APB_M_0_pwdata => s_apb_pwdata,
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APB_M_0_pwrite => s_apb_pwrite,
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IRQ_F2P => s_irq,
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S_AXI_HP0_0_araddr => s_axi_araddr,
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S_AXI_HP0_0_arburst => s_axi_arburst,
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S_AXI_HP0_0_arcache => s_axi_arcache,
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S_AXI_HP0_0_arid => s_axi_arid,
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S_AXI_HP0_0_arlen => s_axi_arlen,
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S_AXI_HP0_0_arlock => s_axi_arlock,
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S_AXI_HP0_0_arprot => s_axi_arprot,
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S_AXI_HP0_0_arqos => s_axi_arqos,
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S_AXI_HP0_0_arready => s_axi_arready,
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S_AXI_HP0_0_arsize => s_axi_arsize,
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S_AXI_HP0_0_arvalid => s_axi_arvalid,
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S_AXI_HP0_0_awaddr => s_axi_awaddr,
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S_AXI_HP0_0_awburst => s_axi_awburst,
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S_AXI_HP0_0_awcache => s_axi_awcache,
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S_AXI_HP0_0_awid => s_axi_awid,
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S_AXI_HP0_0_awlen => s_axi_awlen,
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S_AXI_HP0_0_awlock => s_axi_awlock,
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S_AXI_HP0_0_awprot => s_axi_awprot,
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S_AXI_HP0_0_awqos => s_axi_awqos,
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S_AXI_HP0_0_awready => s_axi_awready,
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S_AXI_HP0_0_awsize => s_axi_awsize,
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S_AXI_HP0_0_awvalid => s_axi_awvalid,
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S_AXI_HP0_0_bid => s_axi_bid,
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S_AXI_HP0_0_bready => s_axi_bready,
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S_AXI_HP0_0_bresp => s_axi_bresp,
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S_AXI_HP0_0_bvalid => s_axi_bvalid,
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S_AXI_HP0_0_rdata => s_axi_rdata,
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S_AXI_HP0_0_rid => s_axi_rid,
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S_AXI_HP0_0_rlast => s_axi_rlast,
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S_AXI_HP0_0_rready => s_axi_rready,
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S_AXI_HP0_0_rresp => s_axi_rresp,
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S_AXI_HP0_0_rvalid => s_axi_rvalid,
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S_AXI_HP0_0_wdata => s_axi_wdata,
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S_AXI_HP0_0_wid => s_axi_wid,
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S_AXI_HP0_0_wlast => s_axi_wlast,
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S_AXI_HP0_0_wready => s_axi_wready,
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S_AXI_HP0_0_wstrb => s_axi_wstrb,
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S_AXI_HP0_0_wvalid => s_axi_wvalid
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);
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-- Memory-mapped registers.
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inst_registers: entity work.registers
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port map (
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clk => clk_adc,
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reset => s_reset,
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apb_psel => s_apb_psel,
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apb_penable => s_apb_penable,
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apb_pwrite => s_apb_pwrite,
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apb_paddr => s_apb_paddr,
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apb_pwdata => s_apb_pwdata,
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apb_pready => s_apb_pready,
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apb_pslverr => s_apb_pslverr,
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apb_prdata => s_apb_prdata,
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reg_control => s_reg_control,
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reg_status => s_reg_status,
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reg_trigger => s_reg_trigger
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);
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-- AXI master.
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inst_axi_master: entity work.dma_axi_master
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generic map (
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transfer_size => 16,
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num_read_channels => 1,
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num_write_channels => 1 )
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port map (
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clk => clk_adc,
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reset => s_reset,
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dma_en => s_reg_control.dma_en,
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dma_busy => s_reg_status.dma_busy,
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window_base_addr => s_reg_control.dma_buf_addr,
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window_size => s_reg_control.dma_buf_size,
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err_read => s_reg_status.dma_err_read,
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err_write => s_reg_status.dma_err_write,
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err_address => s_reg_status.dma_err_address,
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err_any => s_reg_status.dma_err_any,
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clear_errors => s_reg_trigger.dma_clear,
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read_cmd_addr(0) => s_dma_read_cmd_addr,
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read_cmd_valid(0) => s_dma_read_cmd_valid,
|
||
|
|
read_cmd_ready(0) => s_dma_read_cmd_ready,
|
||
|
|
read_data(0) => s_dma_read_data,
|
||
|
|
read_data_valid(0) => s_dma_read_data_valid,
|
||
|
|
write_cmd_addr(0) => s_dma_write_cmd_addr,
|
||
|
|
write_cmd_valid(0) => s_dma_write_cmd_valid,
|
||
|
|
write_cmd_ready(0) => s_dma_write_cmd_ready,
|
||
|
|
write_data(0) => s_dma_write_data,
|
||
|
|
write_data_ready(0) => s_dma_write_data_ready,
|
||
|
|
write_finished(0) => s_dma_write_finished,
|
||
|
|
m_axi_awid => s_axi_awid,
|
||
|
|
m_axi_awaddr => s_axi_awaddr,
|
||
|
|
m_axi_awlen => s_axi_awlen,
|
||
|
|
m_axi_awsize => s_axi_awsize,
|
||
|
|
m_axi_awburst => s_axi_awburst,
|
||
|
|
m_axi_awlock => s_axi_awlock,
|
||
|
|
m_axi_awcache => s_axi_awcache,
|
||
|
|
m_axi_awprot => s_axi_awprot,
|
||
|
|
m_axi_awqos => s_axi_awqos,
|
||
|
|
m_axi_awvalid => s_axi_awvalid,
|
||
|
|
m_axi_awready => s_axi_awready,
|
||
|
|
m_axi_wid => s_axi_wid,
|
||
|
|
m_axi_wdata => s_axi_wdata,
|
||
|
|
m_axi_wstrb => s_axi_wstrb,
|
||
|
|
m_axi_wlast => s_axi_wlast,
|
||
|
|
m_axi_wvalid => s_axi_wvalid,
|
||
|
|
m_axi_wready => s_axi_wready,
|
||
|
|
m_axi_bid => s_axi_bid,
|
||
|
|
m_axi_bresp => s_axi_bresp,
|
||
|
|
m_axi_bvalid => s_axi_bvalid,
|
||
|
|
m_axi_bready => s_axi_bready,
|
||
|
|
m_axi_arid => s_axi_arid,
|
||
|
|
m_axi_araddr => s_axi_araddr,
|
||
|
|
m_axi_arlen => s_axi_arlen,
|
||
|
|
m_axi_arsize => s_axi_arsize,
|
||
|
|
m_axi_arburst => s_axi_arburst,
|
||
|
|
m_axi_arlock => s_axi_arlock,
|
||
|
|
m_axi_arcache => s_axi_arcache,
|
||
|
|
m_axi_arprot => s_axi_arprot,
|
||
|
|
m_axi_arqos => s_axi_arqos,
|
||
|
|
m_axi_arvalid => s_axi_arvalid,
|
||
|
|
m_axi_arready => s_axi_arready,
|
||
|
|
m_axi_rid => s_axi_rid,
|
||
|
|
m_axi_rdata => s_axi_rdata,
|
||
|
|
m_axi_rresp => s_axi_rresp,
|
||
|
|
m_axi_rlast => s_axi_rlast,
|
||
|
|
m_axi_rvalid => s_axi_rvalid,
|
||
|
|
m_axi_rready => s_axi_rready
|
||
|
|
);
|
||
|
|
|
||
|
|
-- little test machine for DMA
|
||
|
|
inst_mem: xpm_memory_sdpram
|
||
|
|
generic map (
|
||
|
|
CLOCKING_MODE => "common_clock",
|
||
|
|
MEMORY_PRIMITIVE => "block",
|
||
|
|
MEMORY_SIZE => 1024 * 64,
|
||
|
|
ADDR_WIDTH_A => 10,
|
||
|
|
ADDR_WIDTH_B => 10,
|
||
|
|
WRITE_DATA_WIDTH_A => 64,
|
||
|
|
BYTE_WRITE_WIDTH_A => 64,
|
||
|
|
READ_DATA_WIDTH_B => 64,
|
||
|
|
READ_LATENCY_B => 1 )
|
||
|
|
port map (
|
||
|
|
clka => clk_adc,
|
||
|
|
clkb => clk_adc,
|
||
|
|
rstb => s_reset,
|
||
|
|
addra => r_test_waddr,
|
||
|
|
addrb => r_test_raddr,
|
||
|
|
dina => s_dma_read_data,
|
||
|
|
doutb => s_test_dout,
|
||
|
|
ena => s_dma_read_data_valid,
|
||
|
|
enb => s_test_ren,
|
||
|
|
wea => "1",
|
||
|
|
regceb => '1',
|
||
|
|
injectdbiterra => '0',
|
||
|
|
injectsbiterra => '0',
|
||
|
|
sleep => '0' );
|
||
|
|
|
||
|
|
s_dma_write_data <= not s_test_dout;
|
||
|
|
s_test_ren <= r_test_prefetch or s_dma_write_data_ready;
|
||
|
|
|
||
|
|
process (clk_adc) is
|
||
|
|
begin
|
||
|
|
if rising_edge(clk_adc) then
|
||
|
|
r_test_prefetch <= '0';
|
||
|
|
if s_dma_read_cmd_ready = '1' and s_dma_read_cmd_valid = '1' then
|
||
|
|
if unsigned(s_dma_read_cmd_addr) < 1008 then
|
||
|
|
s_dma_read_cmd_addr <= std_logic_vector(unsigned(s_dma_read_cmd_addr) + 16);
|
||
|
|
else
|
||
|
|
s_dma_read_cmd_valid <= '0';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
if s_dma_read_data_valid = '1' then
|
||
|
|
s_reg_status.rcnt <= s_reg_status.rcnt + 1;
|
||
|
|
r_test_waddr <= std_logic_vector(unsigned(r_test_waddr) + 1);
|
||
|
|
if unsigned(r_test_waddr) = 1023 then
|
||
|
|
s_dma_write_cmd_valid <= '1';
|
||
|
|
r_test_prefetch <= '1';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
if s_dma_write_cmd_ready = '1' and s_dma_write_cmd_valid = '1' then
|
||
|
|
if unsigned(s_dma_write_cmd_addr) < 1008 then
|
||
|
|
s_dma_write_cmd_addr <= std_logic_vector(unsigned(s_dma_write_cmd_addr) + 16);
|
||
|
|
else
|
||
|
|
s_dma_write_cmd_valid <= '0';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
if (r_test_prefetch = '1') or (s_dma_write_data_ready = '1') then
|
||
|
|
r_test_raddr <= std_logic_vector(unsigned(r_test_raddr) + 1);
|
||
|
|
end if;
|
||
|
|
if s_dma_write_finished = '1' then
|
||
|
|
s_reg_status.wcnt <= s_reg_status.wcnt + 1;
|
||
|
|
end if;
|
||
|
|
if s_reg_trigger.start = '1' then
|
||
|
|
r_test_waddr <= (others => '0');
|
||
|
|
r_test_raddr <= (others => '0');
|
||
|
|
s_dma_read_cmd_addr <= (others => '0');
|
||
|
|
s_dma_write_cmd_addr <= (others => '0');
|
||
|
|
s_dma_read_cmd_valid <= '1';
|
||
|
|
s_dma_write_cmd_valid <= '0';
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
-- END test
|
||
|
|
|
||
|
|
process (clk_fclk) is
|
||
|
|
begin
|
||
|
|
if rising_edge(clk_fclk) then
|
||
|
|
r_fclk_cnt <= r_fclk_cnt + 1;
|
||
|
|
r_fclk_led <= r_fclk_cnt(r_fclk_cnt'high);
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
process (clk_adc) is
|
||
|
|
begin
|
||
|
|
if rising_edge(clk_adc) then
|
||
|
|
r_adcclk_cnt <= r_adcclk_cnt + 1;
|
||
|
|
r_adcclk_led <= r_adcclk_cnt(r_adcclk_cnt'high);
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
end architecture;
|