92 lines
3.0 KiB
Tcl
92 lines
3.0 KiB
Tcl
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#
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# TCL script to build PuzzleFW firmware image
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# for Red Pitaya 4-inputimage in non-project mode.
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#
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# Usage:
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# vivado -mode batch -source nonproject_4ch.tcl
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#
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# Specify FPGA type.
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# This is used by "synth_design".
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set_part xc7z020clg400-1
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## Specify path to RedPitaya board definition.
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## Unclear whether this is required.
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#set_param board.repoPaths [list "RedPitaya-FPGA/brd"]
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# Specify HDL language.
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# This determines the language of the HDL wrapper for the block design.
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set_property target_language VHDL [current_project]
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# Load VHDL files.
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read_vhdl -vhdl2008 ../rtl/puzzlefw_pkg.vhd
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read_vhdl -vhdl2008 ../rtl/acquisition_chain.vhd
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read_vhdl -vhdl2008 ../rtl/acquisition_manager.vhd
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read_vhdl -vhdl2008 ../rtl/acquisition_stream.vhd
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read_vhdl -vhdl2008 ../rtl/adc_capture_ddr.vhd
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read_vhdl -vhdl2008 ../rtl/adc_range_monitor.vhd
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read_vhdl -vhdl2008 ../rtl/adc_sample_stream.vhd
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read_vhdl -vhdl2008 ../rtl/deglitch.vhd
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read_vhdl -vhdl2008 ../rtl/dma_axi_master.vhd
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read_vhdl -vhdl2008 ../rtl/dma_write_channel.vhd
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read_vhdl -vhdl2008 ../rtl/registers.vhd
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read_vhdl -vhdl2008 ../rtl/sample_decimation.vhd
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read_vhdl -vhdl2008 ../rtl/shift_engine.vhd
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read_vhdl -vhdl2008 ../rtl/ffpair.vhd
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read_vhdl -vhdl2008 ../rtl/simple_fifo.vhd
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read_vhdl -vhdl2008 ../rtl/timestamp_gen.vhd
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read_vhdl -vhdl2008 ../rtl/timetagger.vhd
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read_vhdl -vhdl2008 ../rtl/trigger_detector.vhd
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read_vhdl -vhdl2008 ../rtl/puzzlefw_top_4ch.vhd
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# Load Zynq block design.
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#
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# Note: The attribute "synth_flow_mode" in the block design file
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# MUST be set to "None". The default value is "Hierarchical", but that
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# causes problems with synthesis of the IP cores used in the block design.
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#
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# Note: The attribute "gen_directory" in the block design file
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# determines the location of output produced by "generate_target".
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# It must be set to a relative path within the project directory.
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#
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read_bd redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
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set_property synth_checkpoint_mode none [get_files puzzlefw.bd]
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generate_target all [get_files puzzlefw.bd]
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# Load generated HDL wrapper for block design.
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read_vhdl redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd
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# Load constraints.
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read_xdc ../constraints/red_pitaya_4ch.xdc
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# Run synthesis and implementation.
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set outdir output_4ch
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file mkdir $outdir
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synth_design -top puzzlefw_top_4ch
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report_utilization -file $outdir/post_synth_utilization.rpt
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opt_design
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place_design
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report_io -file $outdir/post_place_io.rpt
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phys_opt_design
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route_design
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write_checkpoint -force $outdir/post_route.dcp
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report_drc -file $outdir/post_route_drc.rpt
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report_utilization -file $outdir/post_route_utilization.rpt
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report_timing_summary -file $outdir/post_route_timing.rpt
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report_power -file $outdir/post_route_power.rpt
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report_datasheet -file $outdir/post_route_datasheet.rpt
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# Write .bit file.
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write_bitstream -force $outdir/puzzlefw_top_4ch.bit
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# Export XSA file.
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# This MUST be done via a checkpoint file.
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open_checkpoint $outdir/post_route.dcp
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write_hw_platform -fixed -force -file $outdir/redpitaya_puzzlefw_4ch.xsa
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