62 lines
1.4 KiB
VHDL
62 lines
1.4 KiB
VHDL
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--
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-- Capture ADC sample data from FPGA input ports.
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--
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-- Input signals are captured on the rising edge of CLK.
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-- This entity adds 2 clock cycles delay.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity adc_capture is
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Input signals.
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in_data: in std_logic_vector(adc_data_bits - 1 downto 0);
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-- Output sample stream.
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-- Produces one new ADC sample per clock cycle.
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out_data: out adc_data_type
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);
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end entity;
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architecture arch of adc_capture is
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signal r_stage1: std_logic_vector(adc_data_bits - 1 downto 0);
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signal r_stage2: std_logic_vector(adc_data_bits - 1 downto 0);
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begin
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-- Drive output ports.
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out_data <= r_stage2;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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-- Capture input signals into registers.
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-- These registers will be placed in IO flipflops through IOB constraints.
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r_stage1 <= in_data;
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-- Second register stage.
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-- These can be placed anywhere in the FPGA to optimize timing.
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r_stage2 <= r_stage1;
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end if;
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end process;
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end architecture;
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