Sine/cosine function core in VHDL

Joris van Rantwijk 2dbc6d44db * Reduce width of sin/cos input to multiplier by 1 bit. ... * This has no significant effect on accuracy, but reduces multiplier width.		2016-04-14 00:05:52 +02:00
rtl	* Reduce width of sin/cos input to multiplier by 1 bit.	2016-04-14 00:05:52 +02:00
sim	Full (all-input) test bench for sincos_gen_d18_p20.	2016-04-10 01:26:05 +02:00