vhdl-sincos-gen/rtl
Joris van Rantwijk 2dbc6d44db * Reduce width of sin/cos input to multiplier by 1 bit.
* This has no significant effect on accuracy, but reduces multiplier width.
2016-04-14 00:05:52 +02:00
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sincos_gen.vhdl * Reduce width of sin/cos input to multiplier by 1 bit. 2016-04-14 00:05:52 +02:00
sincos_gen_d18_p20.vhdl Document latency of sincos core. 2016-04-10 01:27:24 +02:00