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vhdl-sincos-gen
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Sine/cosine function core in VHDL
14 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk 15518ce6f7 * Add test-bench for superficial check of 24-bit sine generator. 
* Minor improvement in test-bench for 18-bit sine generator.
 		2016-04-14 23:06:21 +02:00
rtl * Add wrapper for 24-bit sine generator. 2016-04-14 22:53:40 +02:00
sim * Add test-bench for superficial check of 24-bit sine generator. 2016-04-14 23:06:21 +02:00