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vhdl-sincos-gen
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3 Commits

Author SHA1 Message Date
Joris van Rantwijk 15518ce6f7 * Add test-bench for superficial check of 24-bit sine generator. 
* Minor improvement in test-bench for 18-bit sine generator.
 2016-04-14 23:06:21 +02:00
Joris van Rantwijk e8fdb3cff1 Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00
Joris van Rantwijk 7703971a4d Add Makefile for simulation with GHDL. 2016-03-24 23:55:32 +01:00