 Joris van Rantwijk
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cf4e802edf
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* Add comment in simulation Makefile.
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2016-04-16 22:18:41 +02:00 |
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Joris van Rantwijk
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aa8f0217d3
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* Full (all-input) test bench for sincos_gen_d18_p20.
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2016-04-14 23:56:19 +02:00 |
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Joris van Rantwijk
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15518ce6f7
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* Add test-bench for superficial check of 24-bit sine generator.
* Minor improvement in test-bench for 18-bit sine generator.
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2016-04-14 23:06:21 +02:00 |
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Joris van Rantwijk
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e8fdb3cff1
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Full (all-input) test bench for sincos_gen_d18_p20.
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2016-04-10 01:26:05 +02:00 |
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Joris van Rantwijk
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7703971a4d
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Add Makefile for simulation with GHDL.
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2016-03-24 23:55:32 +01:00 |