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* Add accuracy of 24-bit sine generator based on simulation results.

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Joris van Rantwijk 2016-04-19 23:55:31 +02:00
parent 0b723c1599
commit dcdac2e0af
1 changed files with 17 additions and 17 deletions
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README.txt
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@ -105,32 +105,32 @@ These two wrappers are the only tested variants of the core.
Accuracy of the sine/cosine output from the cores has been determined from Accuracy of the sine/cosine output from the cores has been determined from
a simulation of the VHDL code on all possible phase input values. a simulation of the VHDL code on all possible phase input values.
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Core variant sincos_gen_d18_p20 sincos_gen_d24_p26 Core variant sincos_gen_d18_p20 sincos_gen_d24_p26
Phase input width 20 bits 26 bits Phase input width 20 bits 26 bits
Sin/cos output width 18 bits 24 bits Sin/cos output width 18 bits 24 bits
Amplitude 131071.008033 lsb Amplitude 131071.008033 lsb 8388606.997478 lsb
Offset 0.000000 lsb Offset 0.000000 lsb 0.000000 lsb
Phase mismatch 1.30e-7 rad Phase mismatch 1.30e-7 rad 1.99e-9 rad
Peak absolute error 0.966104 lsb Peak absolute error 0.966104 lsb 1.029916 lsb
Root-mean-square error 0.330982 lsb rms Root-mean-square error 0.330982 lsb rms 0.332547 lsb rms
SINAD 108.94 dB SINAD 108.94 dB 145.03 dB
Effective nr of bits 17.80 bits Effective nr of bits 17.80 bits 23.80 bits
Spurious-free dynamic range 129.81 dB Spurious-free dynamic range 129.81 dB 166.18 dB
cos(x) == sin(x+pi/2) exact match cos(x) == sin(x+pi/2) exact match exact match
sin(x) == - sin(x+pi) exact match sin(x) == - sin(x+pi) exact match exact match
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FPGA resources FPGA resources
-------------- --------------
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FPGA type Xilinx Spartan-6 LX45-3 Xilinx Virtex-7 485T-1 FPGA type Xilinx Spartan-6 LX45-3 Xilinx Virtex-7 485T-1
Synthesizer Xilinx ISE 14.7 Xilinx Vivado 2014.4.1 Synthesizer Xilinx ISE 14.7 Xilinx Vivado 2014.4.1
@ -148,5 +148,5 @@ DSP48A1 2 4
Clock freq 230 MHz 230 MHz 400 MHz 400 MHz Clock freq 230 MHz 230 MHz 400 MHz 400 MHz
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