From dcdac2e0af267b1cef718d23add5fcb035188b7c Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Tue, 19 Apr 2016 23:55:31 +0200 Subject: [PATCH] * Add accuracy of 24-bit sine generator based on simulation results. --- README.txt | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/README.txt b/README.txt index 6c6c8db..7cbbf81 100644 --- a/README.txt +++ b/README.txt @@ -105,32 +105,32 @@ These two wrappers are the only tested variants of the core. Accuracy of the sine/cosine output from the cores has been determined from a simulation of the VHDL code on all possible phase input values. --- +---- -Core variant sincos_gen_d18_p20 sincos_gen_d24_p26 -Phase input width 20 bits 26 bits -Sin/cos output width 18 bits 24 bits +Core variant sincos_gen_d18_p20 sincos_gen_d24_p26 +Phase input width 20 bits 26 bits +Sin/cos output width 18 bits 24 bits -Amplitude 131071.008033 lsb -Offset 0.000000 lsb -Phase mismatch 1.30e-7 rad +Amplitude 131071.008033 lsb 8388606.997478 lsb +Offset 0.000000 lsb 0.000000 lsb +Phase mismatch 1.30e-7 rad 1.99e-9 rad -Peak absolute error 0.966104 lsb -Root-mean-square error 0.330982 lsb rms -SINAD 108.94 dB -Effective nr of bits 17.80 bits -Spurious-free dynamic range 129.81 dB +Peak absolute error 0.966104 lsb 1.029916 lsb +Root-mean-square error 0.330982 lsb rms 0.332547 lsb rms +SINAD 108.94 dB 145.03 dB +Effective nr of bits 17.80 bits 23.80 bits +Spurious-free dynamic range 129.81 dB 166.18 dB -cos(x) == sin(x+pi/2) exact match -sin(x) == - sin(x+pi) exact match +cos(x) == sin(x+pi/2) exact match exact match +sin(x) == - sin(x+pi) exact match exact match --- +---- FPGA resources -------------- --- +---- FPGA type Xilinx Spartan-6 LX45-3 Xilinx Virtex-7 485T-1 Synthesizer Xilinx ISE 14.7 Xilinx Vivado 2014.4.1 @@ -148,5 +148,5 @@ DSP48A1 2 4 Clock freq 230 MHz 230 MHz 400 MHz 400 MHz --- +----