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vhdl-sincos-gen
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* Fix mistake in 2nd order Taylor correction. 

* Fix mistake in testbench for 24-bit sine generator.
This commit is contained in:
Joris van Rantwijk 2016-04-14 23:14:58 +02:00
parent 15518ce6f7
commit d2a948f34e
2 changed files with 5 additions and 5 deletions
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4
rtl/sincos_gen.vhdl
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@ -366,9 +366,9 @@ begin
-- sin/cos values for the multiplication.
--
r6_sinm1_a <= r5_sinm2_p(accum_bits-1 downto
r6_sinm1_a <= r5_cosm2_p(accum_bits-1 downto
accum_bits-coeff_bits-1);
r6_cosm1_a <= r5_cosm2_p(accum_bits-1 downto
r6_cosm1_a <= r5_sinm2_p(accum_bits-1 downto
accum_bits-coeff_bits-1);
r6_sinm1_b <= r5_dphase;

6
sim/sim_sincos_d24_p26_probe.vhdl
View File

@ -60,14 +60,14 @@ begin
clk_en <= '1';
-- Probe at a few different inputs.
for i in 0 to input_list'high+6 loop
for i in 0 to input_list'high+9 loop
if i <= input_list'high then
in_phase <= to_unsigned(input_list(i), 26);
end if;
if i >= 6 then
report " phase=" & integer'image(input_list(i-6)) &
if i >= 9 then
report " phase=" & integer'image(input_list(i-9)) &
" sin=" & integer'image(to_integer(out_sin)) &
" cos=" & integer'image(to_integer(out_cos));
end if;