diff --git a/rtl/sincos_gen.vhdl b/rtl/sincos_gen.vhdl
index 3a4a1d1..9b5cb34 100644
--- a/rtl/sincos_gen.vhdl
+++ b/rtl/sincos_gen.vhdl
@@ -366,9 +366,9 @@ begin
                     -- sin/cos values for the multiplication.
                     --
 
-                    r6_sinm1_a  <= r5_sinm2_p(accum_bits-1 downto
+                    r6_sinm1_a  <= r5_cosm2_p(accum_bits-1 downto
                                               accum_bits-coeff_bits-1);
-                    r6_cosm1_a  <= r5_cosm2_p(accum_bits-1 downto
+                    r6_cosm1_a  <= r5_sinm2_p(accum_bits-1 downto
                                               accum_bits-coeff_bits-1);
 
                     r6_sinm1_b  <= r5_dphase;
diff --git a/sim/sim_sincos_d24_p26_probe.vhdl b/sim/sim_sincos_d24_p26_probe.vhdl
index 6a4e53e..5d1bbe1 100644
--- a/sim/sim_sincos_d24_p26_probe.vhdl
+++ b/sim/sim_sincos_d24_p26_probe.vhdl
@@ -60,14 +60,14 @@ begin
         clk_en      <= '1';
 
         -- Probe at a few different inputs.
-        for i in 0 to input_list'high+6 loop
+        for i in 0 to input_list'high+9 loop
 
             if i <= input_list'high then
                 in_phase    <= to_unsigned(input_list(i), 26);
             end if;
 
-            if i >= 6 then
-                report "  phase=" & integer'image(input_list(i-6)) &
+            if i >= 9 then
+                report "  phase=" & integer'image(input_list(i-9)) &
                        " sin=" & integer'image(to_integer(out_sin)) &
                        " cos=" & integer'image(to_integer(out_cos));
             end if;