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vhdl-sincos-gen
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* Further reduction of multiplier width. 

At this point it very slightly affects output quality.
  This change makes it possible to implement up to 24-bit sine generators
  using just 18x18-bit multipliers (i.e. Spartan-6).
This commit is contained in:
Joris van Rantwijk 2016-04-16 09:10:27 +02:00
parent 7ce5b82ff0
commit 8796491f37
1 changed files with 2 additions and 2 deletions
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rtl/sincos_gen.vhdl
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@ -66,10 +66,10 @@ architecture rtl of sincos_gen is
constant dphase_bits: integer := phase_bits - table_addrbits;
-- Number of (MSB) bits from lookup table used for Taylor correction.
constant coeff_bits: integer := table_width + 4 - table_addrbits;
constant coeff_bits: integer := table_width + 3 - table_addrbits;
-- Scaling after Taylor correction.
constant frac_bits: integer := phase_bits + 4 - table_addrbits;
constant frac_bits: integer := phase_bits + coeff_bits - table_width;
constant accum_bits: integer := data_bits + frac_bits;
constant round_const: unsigned(frac_bits-2 downto 0) := (others => '1');