From 8796491f3754dd75318d69b9b4384d48e07b6d29 Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Sat, 16 Apr 2016 09:10:27 +0200 Subject: [PATCH] * Further reduction of multiplier width. At this point it very slightly affects output quality. This change makes it possible to implement up to 24-bit sine generators using just 18x18-bit multipliers (i.e. Spartan-6). --- rtl/sincos_gen.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/sincos_gen.vhdl b/rtl/sincos_gen.vhdl index 9b5cb34..c2f8701 100644 --- a/rtl/sincos_gen.vhdl +++ b/rtl/sincos_gen.vhdl @@ -66,10 +66,10 @@ architecture rtl of sincos_gen is constant dphase_bits: integer := phase_bits - table_addrbits; -- Number of (MSB) bits from lookup table used for Taylor correction. - constant coeff_bits: integer := table_width + 4 - table_addrbits; + constant coeff_bits: integer := table_width + 3 - table_addrbits; -- Scaling after Taylor correction. - constant frac_bits: integer := phase_bits + 4 - table_addrbits; + constant frac_bits: integer := phase_bits + coeff_bits - table_width; constant accum_bits: integer := data_bits + frac_bits; constant round_const: unsigned(frac_bits-2 downto 0) := (others => '1');