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Sine/cosine function core in VHDL
18 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk 8796491f37 * Further reduction of multiplier width. 
At this point it very slightly affects output quality.
  This change makes it possible to implement up to 24-bit sine generators
  using just 18x18-bit multipliers (i.e. Spartan-6).
 		2016-04-16 09:10:27 +02:00
rtl * Further reduction of multiplier width. 2016-04-16 09:10:27 +02:00
sim * Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-14 23:56:19 +02:00
tools * eval_sine_quality.py: Add Python program to evaluate sine waveform. 2016-04-16 09:09:28 +02:00