Joris van Rantwijk 8796491f37 * Further reduction of multiplier width. ... At this point it very slightly affects output quality. This change makes it possible to implement up to 24-bit sine generators using just 18x18-bit multipliers (i.e. Spartan-6).		2016-04-16 09:10:27 +02:00
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sincos_gen.vhdl	* Further reduction of multiplier width.	2016-04-16 09:10:27 +02:00
sincos_gen_d18_p20.vhdl	Document latency of sincos core.	2016-04-10 01:27:24 +02:00
sincos_gen_d24_p26.vhdl	* Add wrapper for 24-bit sine generator.	2016-04-14 22:53:40 +02:00