151 lines
5.1 KiB
VHDL
151 lines
5.1 KiB
VHDL
--
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-- Pseudo Random Number Generator "xoshiro128++ 1.0".
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--
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-- Author: Joris van Rantwijk <joris@jorisvr.nl>
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--
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-- This is a 32-bit random number generator in synthesizable VHDL.
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-- The generator can produce 32 new random bits on every clock cycle.
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--
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-- The algorithm "xoshiro128++" is by David Blackman and Sebastiano Vigna.
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-- See also http://prng.di.unimi.it/
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--
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-- The generator requires a 128-bit seed value, not equal to all zeros.
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-- A default seed must be supplied at compile time and will be used
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-- to initialize the generator at reset. The generator also supports
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-- re-seeding at run time.
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--
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-- After reset and after re-seeding, at least one clock cycle is needed
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-- before valid random data appears on the output.
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--
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-- NOTE: This is not a cryptographic random number generator.
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--
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--
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-- Copyright (C) 2020 Joris van Rantwijk
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- See <https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html>
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rng_xoshiro128plusplus is
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generic (
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-- Default seed value.
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init_seed: std_logic_vector(127 downto 0) );
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port (
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-- Clock, rising edge active.
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clk: in std_logic;
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-- Synchronous reset, active high.
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rst: in std_logic;
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-- High to request re-seeding of the generator.
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reseed: in std_logic;
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-- New seed value (must be valid when reseed = '1').
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newseed: in std_logic_vector(127 downto 0);
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-- High when the user accepts the current random data word
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-- and requests new random data for the next clock cycle.
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out_ready: in std_logic;
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-- High when valid random data is available on the output.
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-- This signal is low during the first clock cycle after reset and
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-- after re-seeding, and high in all other cases.
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out_valid: out std_logic;
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-- Random output data (valid when out_valid = '1').
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-- A new random word appears after every rising clock edge
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-- where out_ready = '1'.
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out_data: out std_logic_vector(31 downto 0) );
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end entity;
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architecture xoshiro128plusplus_arch of rng_xoshiro128plusplus is
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-- Internal state of RNG.
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signal reg_state_s0: std_logic_vector(31 downto 0) := init_seed(31 downto 0);
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signal reg_state_s1: std_logic_vector(31 downto 0) := init_seed(63 downto 32);
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signal reg_state_s2: std_logic_vector(31 downto 0) := init_seed(95 downto 64);
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signal reg_state_s3: std_logic_vector(31 downto 0) := init_seed(127 downto 96);
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-- Output register.
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signal reg_valid: std_logic := '0';
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signal reg_output: std_logic_vector(31 downto 0) := (others => '0');
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begin
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-- Drive output signal.
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out_valid <= reg_valid;
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out_data <= reg_output;
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-- Synchronous process.
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process (clk) is
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begin
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if rising_edge(clk) then
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if out_ready = '1' or reg_valid = '0' then
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-- Prepare output word.
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reg_valid <= '1';
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reg_output <= std_logic_vector(
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rotate_left(unsigned(reg_state_s0) +
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unsigned(reg_state_s3), 7) +
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unsigned(reg_state_s0));
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-- Update internal state.
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reg_state_s0 <= reg_state_s0 xor
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reg_state_s1 xor
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reg_state_s3;
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reg_state_s1 <= reg_state_s0 xor
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reg_state_s1 xor
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reg_state_s2;
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reg_state_s2 <= reg_state_s0 xor
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reg_state_s2 xor
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std_logic_vector(
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shift_left(unsigned(reg_state_s1), 9));
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reg_state_s3 <= std_logic_vector(
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rotate_left(unsigned(reg_state_s1 xor reg_state_s3), 11));
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end if;
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-- Re-seed function.
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if reseed = '1' then
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reg_state_s0 <= newseed(31 downto 0);
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reg_state_s1 <= newseed(63 downto 32);
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reg_state_s2 <= newseed(95 downto 64);
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reg_state_s3 <= newseed(127 downto 96);
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reg_valid <= '0';
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end if;
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-- Synchronous reset.
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if rst = '1' then
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reg_state_s0 <= init_seed(31 downto 0);
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reg_state_s1 <= init_seed(63 downto 32);
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reg_state_s2 <= init_seed(95 downto 64);
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reg_state_s3 <= init_seed(127 downto 96);
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reg_valid <= '0';
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reg_output <= (others => '0');
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end if;
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end if;
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end process;
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end architecture;
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