276 lines
8.8 KiB
VHDL
276 lines
8.8 KiB
VHDL
--
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-- Pseudo Random Number Generator based on Mersenne Twister MT19937.
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--
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-- Author: Joris van Rantwijk <joris@jorisvr.nl>
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--
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-- This is a 32-bit random number generator in synthesizable VHDL.
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-- The generator produces 32 new random bits on every (enabled) clock cycle.
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--
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-- See also M. Matsumoto, T. Nishimura, "Mersenne Twister:
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-- a 623-dimensionally equidistributed uniform pseudorandom number generator",
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-- ACM TOMACS, vol. 8, no. 1, 1998.
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--
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-- The generator requires a 32-bit seed value.
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-- A default seed must be supplied at compile time and will be used
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-- to initialize the generator at reset. The generator also supports
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-- re-seeded at run time.
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--
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-- After reset, and after re-seeding, the generator needs 625 clock
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-- cycles to initialize its internal state. During this time, the generator
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-- is unable to provide correct output.
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--
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-- NOTE: This is not a cryptographic random number generator.
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--
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-- TODO : Multiplication in reseeding severely limits the maximum frequency
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-- for this design.
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-- Add pipelining and increase the number of clock cycles for reseeding.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rng_mt19937 is
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generic (
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-- Default seed value.
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init_seed: std_logic_vector(31 downto 0) );
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port (
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-- Clock, rising edge active.
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clk: in std_logic;
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-- Synchronous reset, active high.
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rst: in std_logic;
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-- High to generate new output value.
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enable: in std_logic;
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-- High to re-seed the generator (works regardless of enable signal).
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reseed: in std_logic;
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-- New seed value (must be valid when reseed = '1').
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newseed: in std_logic_vector(31 downto 0);
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-- Output value.
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-- A new value appears on every rising clock edge where enable = '1'.
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output: out std_logic_vector(31 downto 0);
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-- High while re-seeding (normal function not available).
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busy: out std_logic );
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end entity;
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architecture rng_mt19937_arch of rng_mt19937 is
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-- Constants.
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constant const_a: std_logic_vector(31 downto 0) := x"9908b0df";
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constant const_b: std_logic_vector(31 downto 0) := x"9d2c5680";
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constant const_c: std_logic_vector(31 downto 0) := x"efc60000";
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constant const_f: natural := 1812433253;
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-- Block RAM for generator state.
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type mem_t is array(0 to 620) of std_logic_vector(31 downto 0);
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signal mem: mem_t;
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-- RAM access registers.
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signal reg_a_addr: std_logic_vector(9 downto 0);
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signal reg_b_addr: std_logic_vector(9 downto 0);
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signal reg_a_wdata: std_logic_vector(31 downto 0);
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signal reg_a_rdata: std_logic_vector(31 downto 0);
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signal reg_b_rdata: std_logic_vector(31 downto 0);
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-- Internal registers.
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signal reg_enable: std_logic;
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signal reg_reseeding1: std_logic;
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signal reg_reseeding2: std_logic;
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signal reg_a_wdata_p: std_logic_vector(31 downto 0);
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signal reg_a_rdata_p: std_logic_vector(31 downto 0);
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signal reg_reseed_cnt: std_logic_vector(9 downto 0);
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-- Output register.
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signal reg_output: std_logic_vector(31 downto 0) := (others => '0');
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signal reg_busy: std_logic;
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-- -- Multiply unsigned number with constant and discard overflowing bits.
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-- function mulconst(x: unsigned)
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-- return unsigned
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-- is
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-- variable t: unsigned(2*x'length-1 downto 0);
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-- begin
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-- t := x * const_f;
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-- return t(x'length-1 downto 0);
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-- end function;
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-- Multiply unsigned number with constant and discard overflowing bits.
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function mulconst(x: unsigned)
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return unsigned
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is
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begin
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return x
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+ shift_left(x, 2)
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+ shift_left(x, 5)
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+ shift_left(x, 6)
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+ shift_left(x, 8)
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+ shift_left(x, 11)
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- shift_left(x, 15)
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+ shift_left(x, 19)
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- shift_left(x, 26)
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- shift_left(x, 28)
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+ shift_left(x, 31);
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end function;
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begin
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-- Drive output signal.
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output <= reg_output;
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busy <= reg_busy;
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-- Main synchronous process.
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process (clk) is
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variable y: std_logic_vector(31 downto 0);
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begin
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if rising_edge(clk) then
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-- Update memory pointers.
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if reg_enable = '1' then
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if unsigned(reg_a_addr) = 620 then
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reg_a_addr <= (others => '0');
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else
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reg_a_addr <= std_logic_vector(unsigned(reg_a_addr) + 1);
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end if;
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if unsigned(reg_b_addr) = 620 then
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reg_b_addr <= (others => '0');
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else
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reg_b_addr <= std_logic_vector(unsigned(reg_b_addr) + 1);
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end if;
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end if;
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-- Keep previous values of registers.
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if reg_enable = '1' then
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reg_a_rdata_p <= reg_a_rdata;
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reg_a_wdata_p <= reg_a_wdata;
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end if;
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-- Update reseeding counter.
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reg_reseed_cnt <= std_logic_vector(unsigned(reg_reseed_cnt) + 1);
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-- Determine end of reseeding.
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reg_busy <= reg_reseeding2;
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reg_reseeding2 <= reg_reseeding1;
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if unsigned(reg_reseed_cnt) = 623 then
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reg_reseeding1 <= '0';
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end if;
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-- Enable state machine on next cycle
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-- a) during initialization, and
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-- b) on-demand for new output.
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reg_enable <= reg_reseeding2 or enable;
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-- Update internal RNG state.
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if reg_enable = '1' then
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if reg_reseeding1 = '1' then
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-- Continue re-seeding loop.
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y := reg_a_wdata;
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y(1 downto 0) := y(1 downto 0) xor y(31 downto 30);
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reg_a_wdata <= std_logic_vector(
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mulconst(unsigned(y)) +
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unsigned(reg_reseed_cnt) );
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else
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-- Normal operation.
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-- Perform one step of the "twist" function.
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y := reg_a_rdata_p(31 downto 31) &
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reg_a_rdata(30 downto 0);
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if y(0) = '1' then
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y := "0" & y(31 downto 1);
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y := y xor const_a;
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else
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y := "0" & y(31 downto 1);
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end if;
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reg_a_wdata_p <= reg_a_wdata;
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reg_a_wdata <= reg_b_rdata xor y;
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end if;
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end if;
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-- Produce output value (when enabled).
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if enable = '1' then
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if reg_enable = '1' then
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y := reg_a_wdata;
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else
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y := reg_a_wdata_p;
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end if;
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y(20 downto 0) := y(20 downto 0) xor y(31 downto 11);
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y(31 downto 7) := y(31 downto 7) xor
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(y(24 downto 0) and const_b(31 downto 7));
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y(31 downto 15) := y(31 downto 15) xor
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(y(16 downto 0) and const_c(31 downto 15));
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y(13 downto 0) := y(13 downto 0) xor y(31 downto 18);
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reg_output <= y;
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end if;
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-- Start re-seeding.
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if reseed = '1' then
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reg_reseeding1 <= '1';
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reg_reseeding2 <= '1';
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reg_reseed_cnt <= std_logic_vector(to_unsigned(1, 10));
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reg_enable <= '1';
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reg_a_wdata <= newseed;
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reg_busy <= '1';
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end if;
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-- Synchronous reset.
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if rst = '1' then
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reg_a_addr <= std_logic_vector(to_unsigned(0, 10));
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reg_b_addr <= std_logic_vector(to_unsigned(396, 10));
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reg_reseeding1 <= '1';
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reg_reseeding2 <= '1';
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reg_reseed_cnt <= std_logic_vector(to_unsigned(1, 10));
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reg_enable <= '1';
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reg_a_wdata <= init_seed;
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reg_output <= (others => '0');
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reg_busy <= '1';
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end if;
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end if;
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end process;
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-- Synchronous process for block RAM.
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process (clk) is
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begin
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if rising_edge(clk) then
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if reg_enable = '1' then
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-- Read from port A.
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reg_a_rdata <= mem(to_integer(unsigned(reg_a_addr)));
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-- Read from port B.
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reg_b_rdata <= mem(to_integer(unsigned(reg_b_addr)));
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-- Write to port A.
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mem(to_integer(unsigned(reg_a_addr))) <= reg_a_wdata;
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end if;
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end if;
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end process;
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end architecture;
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