151 lines
4.5 KiB
VHDL
151 lines
4.5 KiB
VHDL
--
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-- Pseudo Random Number Generator "xoroshiro128+".
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--
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-- Author: Joris van Rantwijk <joris@jorisvr.nl>
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--
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-- This is a 64-bit random number generator in synthesizable VHDL.
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-- The generator produces 64 new random bits on every (enabled) clock cycle.
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--
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-- The algorithm "xoroshiro128+" is by David Blackman and Sebastiano Vigna.
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-- See also http://xoroshiro.di.unimi.it/
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--
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-- The generator requires a 128-bit seed value, not equal to zero.
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-- A default seed must be supplied at compile time and will be used
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-- to initialize the generator at reset. The generator also supports
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-- re-seeding at run time.
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--
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-- After reset, at least one clock cycle is needed before valid
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-- random data appears on the output.
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--
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-- NOTE: This is not a cryptographic random number generator.
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--
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-- NOTE: The least significant output bit is less random than
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-- all other output bits.
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--
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--
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-- Copyright (C) 2016 Joris van Rantwijk
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- See <https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html>
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity xoroshiro128plus is
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generic (
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-- Default seed value.
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init_seed: std_logic_vector(127 downto 0) );
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port (
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-- Clock, rising edge active.
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clk: in std_logic;
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-- Synchronous reset, active high.
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rst: in std_logic;
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-- Clock enable, active high.
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enable: in std_logic;
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-- High to re-seed the generator (requires enable = '1').
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reseed: in std_logic;
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-- New seed value (must be valid when reseed = '1').
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newseed: in std_logic_vector(127 downto 0);
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-- Output value.
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-- A new value appears on every rising clock edge where enable = '1'.
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output: out std_logic_vector(63 downto 0) );
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end entity;
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architecture xoroshiro128plus_arch of xoroshiro128plus is
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-- Internal state of RNG.
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signal reg_state_s0: std_logic_vector(63 downto 0) := init_seed(63 downto 0);
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signal reg_state_s1: std_logic_vector(63 downto 0) := init_seed(127 downto 64);
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-- Output register.
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signal reg_output: std_logic_vector(63 downto 0) := (others => '0');
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-- Shift left.
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function shiftl(x: std_logic_vector; b: integer)
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return std_logic_vector
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is
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constant n: integer := x'length;
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variable y: std_logic_vector(n-1 downto 0);
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begin
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y(n-1 downto b) := x(x'high-b downto x'low);
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y(b-1 downto 0) := (others => '0');
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return y;
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end function;
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-- Rotate left.
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function rotl(x: std_logic_vector; b: integer)
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return std_logic_vector
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is
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constant n: integer := x'length;
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variable y: std_logic_vector(n-1 downto 0);
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begin
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y(n-1 downto b) := x(x'high-b downto x'low);
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y(b-1 downto 0) := x(x'high downto x'high-b+1);
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return y;
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end function;
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begin
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-- Drive output signal.
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output <= reg_output;
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-- Synchronous process.
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process (clk) is
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begin
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if rising_edge(clk) then
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if enable = '1' then
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-- Prepare output word.
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reg_output <= std_logic_vector(unsigned(reg_state_s0) +
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unsigned(reg_state_s1));
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-- Update internal state.
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reg_state_s0 <= reg_state_s0 xor
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reg_state_s1 xor
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shiftl(reg_state_s0, 14) xor
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shiftl(reg_state_s1, 14) xor
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rotl(reg_state_s0, 55);
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reg_state_s1 <= rotl(reg_state_s0, 36) xor
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rotl(reg_state_s1, 36);
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-- Re-seed function.
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if reseed = '1' then
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reg_state_s0 <= newseed(63 downto 0);
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reg_state_s1 <= newseed(127 downto 64);
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end if;
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end if;
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-- Synchronous reset.
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if rst = '1' then
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reg_state_s0 <= init_seed(63 downto 0);
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reg_state_s1 <= init_seed(127 downto 64);
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reg_output <= (others => '0');
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end if;
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end if;
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end process;
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end architecture;
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