Another possible improvement of MT19937 timing.
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@ -34,10 +34,6 @@
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-- See <https://www.gnu.org/licenses/old-licenses/lgpl-2.1.html>
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--
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-- TODO : Multiplication in reseeding severely limits the maximum frequency
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-- for this design.
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-- Add pipelining and increase the number of clock cycles for reseeding.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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@ -115,8 +111,9 @@ architecture rng_mt19937_arch of rng_mt19937 is
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signal reg_seed_a: std_logic_vector(31 downto 0);
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signal reg_seed_b: std_logic_vector(31 downto 0);
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signal reg_seed_b2: std_logic_vector(31 downto 0);
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signal reg_seed_b3: std_logic_vector(31 downto 0);
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signal reg_seed_c: std_logic_vector(31 downto 0);
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signal reg_seed_c2: std_logic_vector(31 downto 0);
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signal reg_seed_d: std_logic_vector(31 downto 0);
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-- Output register.
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signal reg_valid: std_logic;
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@ -186,28 +183,26 @@ begin
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end if;
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-- Enable state machine on next cycle
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-- a) every 4th cycle during initialization, and
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-- a) every 1st out of 4 cycles during reseeding, and
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-- b) on-demand for new output.
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reg_enable <= reg_reseedstate(2) or
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reg_enable <= reg_reseedstate(3) or
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(not reg_reseeding and
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(out_ready or not reg_valid));
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-- Reseed state 1: XOR and shift previous state element.
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if reg_reseeding = '1' then
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y := reg_a_wdata;
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y := reg_seed_d;
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y(1 downto 0) := y(1 downto 0) xor y(31 downto 30);
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reg_seed_a <= y;
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end if;
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-- Reseed state 2: Multiply by constant.
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if force_const_mul then
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-- Multiply by 37.
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reg_seed_b2 <= std_logic_vector(
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reg_seed_b <= std_logic_vector(
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unsigned(reg_seed_a)
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+ shift_left(unsigned(reg_seed_a), 2)
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+ shift_left(unsigned(reg_seed_a), 5));
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-- Multiply by (2**19 - 2**15).
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reg_seed_b3 <= std_logic_vector(
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reg_seed_b2 <= std_logic_vector(
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shift_left(unsigned(reg_seed_a), 19)
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- shift_left(unsigned(reg_seed_a), 15));
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else
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@ -217,32 +212,40 @@ begin
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mulconst(unsigned(reg_seed_a)));
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end if;
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-- Reseed state 3: Finish multiplication by constant.
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-- Reseed state 3: Continue multiplication by constant.
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if force_const_mul then
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-- Finalize multiplication by 1812433253 =
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-- (37 + 2**6*37 - 2**15 + 2**19 - 2**26*37)
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reg_seed_c <= std_logic_vector(
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unsigned(reg_seed_b2)
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+ shift_left(unsigned(reg_seed_b2), 6)
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+ unsigned(reg_seed_b3)
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- shift_left(unsigned(reg_seed_b2), 26));
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unsigned(reg_seed_b)
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+ shift_left(unsigned(reg_seed_b), 6)
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+ unsigned(reg_seed_b2));
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reg_seed_c2 <= std_logic_vector(
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unsigned(reg_reseed_cnt)
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- shift_left(unsigned(reg_seed_b), 26));
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else
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reg_seed_c <= reg_seed_b;
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end if;
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-- TODO : try this in synthesis;
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-- if not good enough, use state 4 to combine the last add step
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-- with the final add of reg_reseed_cnt, then put that directly
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-- into reg_a_wdata and into next seeding step.
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-- Reseed state 4: Prepare next element of initial state.
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if reg_reseeding = '1' then
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-- Add result of multiplication to reseed counter.
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if force_const_mul then
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reg_seed_d <= std_logic_vector(unsigned(reg_seed_c) +
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unsigned(reg_seed_c2));
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else
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reg_seed_d <= std_logic_vector(unsigned(reg_seed_c) +
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unsigned(reg_reseed_cnt));
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end if;
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end if;
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-- Update internal RNG state.
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if reg_enable = '1' then
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if reg_reseeding = '1' then
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-- Reseed state 4: Write next state element.
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reg_a_wdata <= std_logic_vector(unsigned(reg_seed_c) +
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unsigned(reg_reseed_cnt));
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-- Reseed state 1: Write next state element.
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reg_a_wdata <= reg_seed_d;
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else
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@ -300,9 +303,9 @@ begin
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if reseed = '1' then
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reg_reseeding <= '1';
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reg_reseedstate <= "0001";
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reg_reseed_cnt <= std_logic_vector(to_unsigned(1, 10));
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reg_enable <= '0';
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reg_a_wdata <= newseed;
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reg_reseed_cnt <= std_logic_vector(to_unsigned(0, 10));
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reg_enable <= '1';
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reg_seed_d <= newseed;
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reg_valid <= '0';
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end if;
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@ -312,9 +315,9 @@ begin
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reg_b_addr <= std_logic_vector(to_unsigned(396, 10));
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reg_reseeding <= '1';
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reg_reseedstate <= "0001";
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reg_reseed_cnt <= std_logic_vector(to_unsigned(1, 10));
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reg_enable <= '0';
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reg_a_wdata <= init_seed;
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reg_reseed_cnt <= std_logic_vector(to_unsigned(0, 10));
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reg_enable <= '1';
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reg_seed_d <= init_seed;
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reg_valid <= '0';
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reg_output <= (others => '0');
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end if;
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@ -80,7 +80,7 @@ begin
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s_rst <= '0';
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-- Give generator time to complete initialization.
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for i in 0 to 3*624 loop
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for i in 0 to 4*624 loop
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assert s_valid = '0' report "Generator indicates VALID too early";
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wait until falling_edge(clk);
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end loop;
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@ -133,7 +133,7 @@ begin
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s_newseed <= (others => '0');
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-- Give generator time to complete initialization.
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for i in 0 to 3*624 loop
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for i in 0 to 4*624 loop
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assert s_valid = '0' report "Generator indicates VALID too early";
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wait until falling_edge(clk);
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s_ready <= '1';
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