Trivium: Synthesis testrun.

README.txt

@@ -43,7 +43,7 @@ Seed length:        128 bits
 Period:             2**128 - 1
 
 FPGA resources:     general logic and 64-bit adder
-Sythesis results:   194 LUTs, 192 registers on Spartan-6
+Synthesis results:  194 LUTs, 192 registers on Spartan-6
 Timing results:     333 MHz on Spartan-6 LX45-3
 
 
@@ -80,7 +80,7 @@ Seed length:        32 bits
 Period:             2**19937 - 1
 
 FPGA resources:     RAM block, 32 bits x 1024 elements
-Sythesis results:   279 LUTs, 297 registers, 2x RAMB16 on Spartan-6
+Synthesis results:  279 LUTs, 297 registers, 2x RAMB16 on Spartan-6
 Timing results:     300 MHz on Spartan-6 LX45-3
 
 
@@ -115,8 +115,8 @@ Seed length:        80 bits key + 80 bits IV
 Period:             unknown, depends on seed
 
 FPGA resources:     only general logic (AND, XOR ports, registers)
-Sythesis results:   TBD LUTs, TBD registers on Spartan-6 (32 bits output)
-Timing results:     TBD MHz on Spartan-6 LX45-3 (32 bits output)
+Synthesis results:  202 LUTs, 332 registers on Spartan-6 (32 bits output)
+Timing results:     380 MHz on Spartan-6 LX45-3 (32 bits output)
 
 
   Code organization

synth/top_trivium.vhdl

@@ -0,0 +1,33 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity toptriv is
+    port (
+        clk :   in  std_logic;
+        rst :   in  std_logic;
+        ready:  in  std_logic;
+        valid:  out std_logic;
+        data:   out std_logic_vector(31 downto 0) );
+end toptriv;
+
+architecture arch of toptriv is
+begin
+
+    inst_prng: entity work.rng_trivium
+        generic map (
+            num_bits  => 32,
+            init_key  => x"31415926535897932384",
+            init_iv   => x"0123456789abcdefa50f" )
+        port map (
+            clk       => clk,
+            rst       => rst,
+            reseed    => '0',
+            newkey    => (others => '0'),
+            newiv     => (others => '0'),
+            out_ready => ready,
+            out_valid => valid,
+            out_data  => data );
+
+end arch;
+