Sine/cosine function core in VHDL
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Joris van Rantwijk aa8f0217d3 * Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-14 23:56:19 +02:00
rtl * Fix mistake in 2nd order Taylor correction. 2016-04-14 23:14:58 +02:00
sim * Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-14 23:56:19 +02:00