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vhdl-sincos-gen
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Sine/cosine function core in VHDL
9 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk 9f4bb7f9b0 * Increase precision of delta_phase term by 1 bit. 
* This improves accuracy of 1st order Taylor variant to less than 1.0 lsb peak deviation.
* Add comments.
 		2016-04-13 23:32:02 +02:00
rtl * Increase precision of delta_phase term by 1 bit. 2016-04-13 23:32:02 +02:00
sim Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00