111 lines
2.8 KiB
VHDL
111 lines
2.8 KiB
VHDL
--
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-- Test sine / cosine function core on Digilent Atlys board.
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--
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--
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-- Serial port protocol (via USB):
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--
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-- * Baud rate 115200
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--
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-- * Send 6 bytes
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-- { 0x41 0x42 phase(7:0) phase(15:8) phase(23:16) phase(31:24) }
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-- to calculate sine and cosine of phase on the 18-bit / 20-bit core.
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-- Board answers with 8 bytes
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-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24)
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-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 }
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--
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-- * Send 6 bytes
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-- { 0x41 0x43 phase(7:0) phase(15:8) phase(23:16) phase(31:24) }
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-- to calculate sine and cosine of phase on the 24-bit / 26-bit core.
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-- Board answers with 8 bytes
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-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24)
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-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 }
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--
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-- * Send 2 bytes { 0x41 0x44 } to start clock-enable modulation.
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--
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-- * Send 3 bytes { 0x41 0x45 } to stop clock-enable modulation.
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--
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-- Status LEDs:
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-- LED 0 = Ready (waiting for command)
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-- LED 1 = Calculating
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-- LED 2 = Clock-enable modulation active
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-- LED 3 = Transmitting
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--
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-- AC97 audio:
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-- not yet implemented
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity top_test_sincos is
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port (
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-- 100 MHz system clock
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clk: in std_logic;
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-- Reset button
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resetn: in std_logic;
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-- Status LEDs
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led: out std_logic_vector(7 downto 0);
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-- Uart
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uartrx: in std_logic;
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uarttx: out std_logic;
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-- AC97 audio
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ac97_bitclk: in std_logic;
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ac97_sdi: in std_logic;
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ac97_sdo: out std_logic;
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ac97_sync: out std_logic;
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ac97_rst: out std_logic );
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end entity;
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architecture rtl of top_test_sincos is
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signal r_rstgen: std_logic_vector(7 downto 0) := "00000000";
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signal r_reset: std_logic;
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begin
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-- Instantiate test design with serial interface.
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u0: entity work.test_sincos_serial
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generic map (
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serial_bitrate_divider => 868 )
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port map (
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clk => clk,
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rst => r_reset,
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ser_rx => uartrx,
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ser_tx => uarttx,
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stat_ready => led(0),
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stat_calc => led(1),
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stat_clkmod => led(2),
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stat_txser => led(3) );
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-- Drive unused LEDs.
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led(7 downto 4) <= "0000";
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-- AC97 not yet implemented
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ac97_sdo <= '0';
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ac97_sync <= '0';
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ac97_rst <= '0';
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-- Reset synchronizer.
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process (clk) is
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begin
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if rising_edge(clk) then
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if resetn = '0' then
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r_rstgen <= (others => '0');
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r_reset <= '1';
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else
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r_rstgen <= "1" & r_rstgen(7 downto 1);
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r_reset <= not r_rstgen(0);
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end if;
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end if;
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end process;
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end architecture;
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