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vhdl-sincos-gen
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9c73463282
vhdl-sincos-gen
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synth
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Joris van Rantwijk
9c73463282
Add top-level test design for Digilent Atlys board.
2016-04-22 09:42:48 +02:00
..
digilent_atlys
Add top-level test design for Digilent Atlys board.
2016-04-22 09:42:48 +02:00
xilinx_spartan6
* New synthesis dry-run for Spartan-6.
2016-04-19 23:36:10 +02:00
xilinx_virtex7
* Add Vivado project files for dry-run on Virtex-7.
2016-04-19 23:36:10 +02:00