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vhdl-sincos-gen
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Sine/cosine function core in VHDL
12 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk 9873f91e8e * Further reduction of multiplier width. 
* Add more comments.
 		2016-04-14 22:49:32 +02:00
rtl * Further reduction of multiplier width. 2016-04-14 22:49:32 +02:00
sim Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00