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vhdl-sincos-gen
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Sine/cosine function core in VHDL
7 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk 7de76c6696 Reduce amplitude to avoid numeric overflow. 2016-04-11 21:28:17 +02:00
rtl Reduce amplitude to avoid numeric overflow. 2016-04-11 21:28:17 +02:00
sim Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00