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vhdl-sincos-gen
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Sine/cosine function core in VHDL
22 Commits 1 Branch 0 Tags 89 KiB
VHDL 88.1%
Python 10.1%
Makefile 1.7%
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Joris van Rantwijk 5e02c373de * Implement serial port interface in test design. 2016-04-18 21:14:31 +02:00
rtl * Implement serial port interface in test design. 2016-04-18 21:14:31 +02:00
sim * Add comment in simulation Makefile. 2016-04-16 22:18:41 +02:00
tools * eval_sine_quality.py: Add Python program to evaluate sine waveform. 2016-04-16 09:09:28 +02:00