Joris van Rantwijk cf4e802edf * Add comment in simulation Makefile.		2016-04-16 22:18:41 +02:00
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Makefile	* Add comment in simulation Makefile.	2016-04-16 22:18:41 +02:00
sim_sincos_d18_p20_full.vhdl	Full (all-input) test bench for sincos_gen_d18_p20.	2016-04-10 01:26:05 +02:00
sim_sincos_d18_p20_probe.vhdl	* Add test-bench for superficial check of 24-bit sine generator.	2016-04-14 23:06:21 +02:00
sim_sincos_d24_p26_full.vhdl	* Full (all-input) test bench for sincos_gen_d18_p20.	2016-04-14 23:56:19 +02:00
sim_sincos_d24_p26_probe.vhdl	* Fix mistake in 2nd order Taylor correction.	2016-04-14 23:14:58 +02:00